Figure 17. Asynchronous Multiplexed Address 16-Bit Read Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

nSELECT
tSS
nDATA_STRB
ADDR_LAT
tAS
MEM_nREG
tAS
CPU_WORD_EN[1:0]
tAS
MSW_nLSW
tAS
RD_nWR
tAS
CPU_DATA
nDATA_RDY

Figure 17. Asynchronous Multiplexed Address 16-bit Read Timing

Figure 17 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle. In
Asynchronous mode, nSELECT may be kept low for consecutive transactions
by the Total-AceXtreme.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be '11' through the full
transfer cycle.
Data Device Corporation
www.ddc-web.com
tALP
tAH
tAH
Address Data A
tDD
tWait tRDD
H O S T I N T E R F A C E
tALP
tAS
tOH
tOHZ tAS tAH
Address
49
tSH
tAH
tAH
tAH
tOH
tOHZ
Data B
tDD
tWait tRDD
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