DDC Total-AceXtreme MIL-STD-1553 Design Manual page 61

AceXtreme memory address; the values of the RD_nWR, MEM_nREG, and
MSW_nLSW (for 16-bit mode only) signals; and, for write transfers only, 32-bit or 16-
bit data.
In Synchronous burst mode, the rate that the command FIFO will fill is equal to the
frequency of HOST_CLK. The command FIFO is drained by internal logic within the
Total-AceXtreme®. For memory transfers, the normal FIFO drain rate is 160 MHz,
however this rate can temporarily drop to a value between 120 to 160 MHz during
internal memory accesses by the Total-AceXtreme's MIL-STD-1553 protocol logic.
However, for register write transfers, the drain rate is 40 MHz.
As a result, the only scenario that can result in a full or near-full command FIFO is
during or immediately following a register burst write transfer (the Total-AceXtreme
does not support register burst read transfers), when the frequency of HOST_CLK is
higher than 40 MHz.
Once the command FIFO fills to capacity, the Total-AceXtreme will assert its
CPU_nSTOP output signal low, and de-assert its nDATA_RDY high. At this time, the
host CPU must terminate its transfer.
To illustrate by example, if the command FIFO size is 32 words, the HOST_CLK
frequency is 80 MHz, and a 32-bit sequential register write burst is performed. In this
example, the command FIFO will fill at 80 MHz and drain at 40 MHz, for a "net fill
rate" of 40 MHz. That is, for every two register words written to the FIFO, only one is
drained. Therefore, after 64 32-bit words have been written by the host to a
previously empty command FIFO, the command FIFO will fill, and the Total-
AceXtreme will assert its CPU_nSTOP output signal (and bring nDATA_RDY high),
thereby terminating the sequential register write burst transfer. The timing for this
scenario is shown in Figure 47.
Once CPU_nSTOP has asserted, it is recommended for the host to delay before
attempting to retry the current multi-word transfer. To ensure that the FIFO has
drained sufficiently, the host should delay for sufficient time to allow at least half of
the words in the FIFO to be drained. Assuming that the FIFO is fully populated with
register write transfer commands, these require 25 ns each to drain. Therefore, the
minimum delay times to prevent a subsequent "STOP" condition are 425 ns for a 32-
word command FIFO; 225 ns for a 16-word command FIFO; and 125 ns for an 8-
word command FIFO.
Another possible scenario that could occur is if the host performs a sequential
register write burst that terminates normally. That is, the command FIFO is not filled
to capacity, and the Total-AceXtreme asserts nDATA_RDY low, while CPU_nSTOP
remains high. In this case, assume a 32-word FIFO that is filled half-way by register
write transfers, and a HOST_CLK frequency of 80 MHz.
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