Table Of Contents - DDC Total-AceXtreme MIL-STD-1553 Design Manual

1 PREFACE ............................................................................................................. 1
1.1 Text Usage .................................................................................................................. 1
1.2 Standard Definitions .................................................................................................... 1
1.3 Trademarks ................................................................................................................. 1
1.4 Technical Support ....................................................................................................... 2
2 OVERVIEW .......................................................................................................... 3
2.1 Features ...................................................................................................................... 3
2.2 Specifications .............................................................................................................. 8
2.3 Additional Support Documents .................................................................................. 12
2.4 Total-AceXtreme® Development Kit .......................................................................... 13
3 MIL-STD-1553 MODES AND ARCHITECTURE ................................................ 15
3.1 Bus Controller Mode.................................................................................................. 15
4 GLOBAL FEATURES ........................................................................................ 22
4.1 Transceivers and Isolation Transformers ................................................................... 22
4.2 Time Tags ................................................................................................................. 22
4.3 Local Timer ............................................................................................................... 22
4.4 DMA Controller .......................................................................................................... 23
5 BUILT-IN TEST .................................................................................................. 25
5.1 Total-AceXtreme® Self-Test ...................................................................................... 25
5.2 JTAG Boundary Scan ................................................................................................ 25
6 HOST INTERFACE ............................................................................................ 27
6.1 Host Interface Configuration Options ......................................................................... 27
6.2 Parallel CPU Interface ............................................................................................... 27
6.3 Asynchronous Interface Mode ................................................................................... 35
6.4 Synchronous Host Processor Interface ..................................................................... 51
6.5 PCI Interface ............................................................................................................. 88
7 POWER INPUTS ................................................................................................ 97
7.1 Decoupling Capacitors .............................................................................................. 97
7.2 Power Sequencing .................................................................................................... 97
8 MIL-STD-1553 TRANSCEIVER OPTIONS ...................................................... 100
8.1 Using the Internal Transceivers ............................................................................... 100
8.2 Using External Fiber Optic Transceivers ................................................................. 102
9 THERMAL MANAGEMENT FOR TOTAL-ACEXTREME ................................ 104
10 REGISTER AND MEMORY ADDRESSING ..................................................... 107
10.1 Memory Address Space .......................................................................................... 107
10.2 Register Address Space .......................................................................................... 107
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