Figure 35. Synchronous, Multiplexed Address 16-Bit Single-Word Memory Write Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
tCS
nSELECT
tSS
nDATA_STRB
tALH
tALS
ADDR_LAT
tAS
CPU_WORD_EN[1:0]
tAS tAH
MEM_nREG
tAS
MSW_nLSW
tAS
RD_nWR
tAS tAH tDS
Address
CPU_DATA
nDATA_RDY
CPU_nSTOP

Figure 35. Synchronous, Multiplexed Address 16-bit Single-Word Memory Write Timing

Figure 35 Notes:
1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for this
data transfer. nSELECT must be asserted through the full transfer cycle, and
de-asserted high at the end of the transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be '11' through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted for write accesses, and will remain high.
Data Device Corporation
www.ddc-web.com
tWait
tCH
tSH
tDH
Data A
tRDD tRDD
H O S T I N T E R F A C E
tWait
tCS
tSH
tSS
tALH
tALS
tAS tAH
tAS
tAS tAH tDS
Address Data B
75
tCH tSHC
tAH
tAH
tAH
tDH
tRDD tRDD
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