DDC Total-AceXtreme MIL-STD-1553 Design Manual page 39

For non-multiplexed random Synchronous burst write transfers, the value of the
first address to be written must be presented on CPU_ADDR(15:0) during the
same host clock cycle that nDATA_STRB is initially asserted low, and driven until
nDATA_RDY is asserted low. After the Total-AceXtreme® asserts its
nDATA_RDY output low, the host must then present a new address on
CPU_ADDR(15:0) for each successive host clock cycle through the end of the
burst transfer.
In 16-bit mode, the host address must be driven on to CPU_ADDR(15:0) during
both the first and second 16-bit transfers.
In the multiplexed address/data mode, CPU_ADDR(15:0) is not used and may be
left unconnected.
• nSELECT:
When asserted low, nSELECT is the "chip select" input to the Total-AceXtreme.
nSELECT must remain asserted through the end of each transfer cycle.
For Asynchronous mode, if the Total-AceXtreme is the only node on the bus,
then nSELECT may be tied to logic '0'.
In Synchronous mode, nSELECT must de-assert high and remain high for one
host clock cycle to end the current transaction, and prior to re-asserting low to
initiate the next transaction.
• MEM_nREG:
This signal selects between accesses to Total-AceXtreme internal memory
(when high) and Total-AceXtreme registers (when low). It must be presented
valid during the same time window as CPU_ADDR(15:0). In the multiplexed
address/data modes, the value of MEM_nREG is latched when the ADDR_LAT
input is asserted high.
• nDATA_STRB:
This active low input signal is the main control signal for the Total-AceXtreme's
CPU interface. Its specific operation varies as a function of Asynchronous vs.
Synchronous mode; and for Synchronous mode, for single-word transfers,
sequential burst transfers, and random burst write transfers. The Total-
AceXtreme does not support Synchronous random burst read transfers.
In Asynchronous mode, nDATA_STRB must be asserted low through the full
data portion of each 32-bit or 16-bit transfer cycle. In Synchronous mode,
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