11.2 Host Interface Signals; Table 18. Pci Signals - DDC Total-AceXtreme MIL-STD-1553 Design Manual

11.2 Host Interface Signals

11.2.1 PCI Signals
Note that most of these signals are dual use. That is, they take on different function,
depending on whether the Total-AceXtreme® is configured for PCI mode or for
FGPI mode.
Signal Name BALL
PCI_AD(31) (I/O) MSB
PCI_AD(30) (I/O)
PCI_AD(29) (I/O)
PCI_AD(28) (I/O)
PCI_AD(27) (I/O)
PCI_AD(26) (I/O)
PCI_AD(25) (I/O)
PCI_AD(24) (I/O)
PCI_AD(23) (I/O)
PCI_AD(22) (I/O)
PCI_AD(21) (I/O)
PCI_AD(20) (I/O)
PCI_AD(19) (I/O)
PCI_AD(18) (I/O)
PCI_AD(17) (I/O)
PCI_AD(16) (I/O)
PCI_AD(15) (I/O)
PCI_AD(14) (I/O)
PCI_AD(13) (I/O)
PCI_AD(12) (I/O)
PCI_AD(11) (I/O)
PCI_AD(10) (I/O)
PCI_AD(09) (I/O)
PCI_AD(08) (I/O)
PCI_AD(07) (I/O)
PCI_AD(06) (I/O)
PCI_AD(05) (I/O)
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Table 18. PCI Signals

Pullup/
Pulldown
A5 None
A4 None
B5 None
B4 None
B3 None
D1 None
C2 None
D3 None
F1 None
E2 None
E3 None
32-Bit PCI Bus Address / Data lines. Address and Data are multiplexed on
F3 None
the same pins. Each bus operation consists of an address phase followed by
one or more data phases.
G1 None
G3 None
Address phases are identified when the control signal FRAME# is asserted.
J5 None Data transfers occur during those clock cycles in which the control signals
IRDY# and TRDY# are both asserted.
H1 None
K1 None
M2 None
L1 None
N1 None
L3 None
K2 None
M1 None
N2 None
N3 None
N4 None
M4 None
T O T A L - A C E X T R E M E ® S I G N A L S
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