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Total-AceXtreme BU-67301B
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Manuals and User Guides for DDC Total-AceXtreme BU-67301B. We have
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DDC Total-AceXtreme BU-67301B manual available for free PDF download: Design Manual
DDC Total-AceXtreme BU-67301B Design Manual (141 pages)
Ultra-Small, Ultra-Low Power Single Package Solution
Brand:
DDC
| Category:
Transceiver
| Size: 7.36 MB
Table of Contents
Table of Contents
5
1 Preface
10
Text Usage
10
Standard Definitions
10
Trademarks
10
Technical Support
11
2 Overview
12
Features
12
Figure 1. BU-67301B Total-Acextreme
15
Figure 2. Total-Acextreme® Block Diagram
16
Specifications
17
Table 1. Total-Acextreme® Series Specifications
17
Additional Support Documents
21
Total-Acextreme® Development Kit
22
3 Mil-Std-1553 Modes and Architecture
24
Bus Controller Mode
24
Figure 3. Bus Controller Block Diagram - Remote Terminal Operation
25
Figure 4. Remote Terminal Block Diagram - Monitor Mode Operation
27
Figure 5. Monitor Block Diagram - Advanced Data Handler (ADH)
28
4 Global Features
31
Transceivers and Isolation Transformers
31
Time Tags
31
Local Timer
31
DMA Controller
32
Figure 6. PCI DMA Block Diagram - Digital I/O
32
5 Built-In Test
34
Total-Acextreme® Self-Test
34
JTAG Boundary Scan
34
Table 2. Supported JTAG Functions
35
6 Host Interface
36
Host Interface Configuration Options
36
Parallel CPU Interface
36
Table 3. Total-Acextreme® Host Interface Configuration Options
37
Table 4. Summary of the Operation of the Ndata_Rdy Output Signal for Synchronous Single-Word Memory and Register Accesses
42
Asynchronous Interface Mode
44
Table 5. Asynchronous 16-Bit Mode Configuration Options
45
Figure 7. 32-Bit, Non-Multiplexed Address, Asynchronous Interface
46
Figure 8. 32-Bit, Multiplexed Address, Asynchronous Interface
47
Figure 9. 16-Bit, Non-Multiplexed Address, Asynchronous Interface
48
Figure 10. 16-Bit, Multiplexed Address, Asynchronous Interface
49
Table 6. Asynchronous Transfers
50
Table 7. Asynchronous Timing Information
50
Figure 11. Asynchronous Non-Multiplexed Address 32-Bit Read Timing
52
Figure 12. Asynchronous Non-Multiplexed Address 32-Bit Write Timing
53
Figure 13. Asynchronous Non-Multiplexed Address 16-Bit Read Timing
54
Figure 14. Asynchronous Non-Multiplexed Address 16-Bit Write Timing
55
Figure 15. Asynchronous Multiplexed Address 32-Bit Read Timing
56
Figure 16. Asynchronous Multiplexed Address 32-Bit Write Timing
57
Figure 17. Asynchronous Multiplexed Address 16-Bit Read Timing
58
Figure 18. Asynchronous Multiplexed Address 16-Bit Write Timing
59
Synchronous Host Processor Interface
60
Table 8. Synchronous 16-Bit Mode Configuration Options
64
Figure 19. 32-Bit, Non-Multiplexed Address, Synchronous Interface
65
Figure 20. 32-Bit, Multiplexed Address, Synchronous Interface
66
Figure 21. 16-Bit, Non-Multiplexed Address, Synchronous Interface
67
Figure 22. 16-Bit, Multiplexed Address, Synchronous Interface
68
Table 9. Single-Word Synchronous Transfers
69
Table 10. Synchronous Burst Transfers
69
Table 11. Synchronous Timing Parameters
70
Figure 23. Synchronous, Non-Multiplexed Address - 32-Bit Single-Word Memory Read Timing
72
Figure 24. Synchronous, Non-Multiplexed Address - 32-Bit Single-Word Register Read Timing
73
Figure 25. Synchronous, Non-Multiplexed Address - 32-Bit Single-Word Write Timing
74
Figure 26. Synchronous, Non-Multiplexed Address 16-Bit - Single-Word Memory Read Timing
75
Figure 27. Synchronous, Non-Multiplexed Address 16-Bit - Single-Word Register Read Timing
76
Figure 28. Synchronous, Non-Multiplexed Address - 16-Bit Single-Word Memory Write Timing
77
Figure 29. Synchronous, Non-Multiplexed Address - 16-Bit Single-Word Register Write Timing
78
Figure 30. Synchronous, Multiplexed Address 32-Bit - Single-Word Memory Read Timing
79
Figure 31. Synchronous, Multiplexed Address 32-Bit - Single-Word Register Read Timing
80
Figure 32. Synchronous, Multiplexed Address 32-Bit Single-Word Write Timing
81
Figure 33. Synchronous, Multiplexed Address 16-Bit - Single-Word Memory Read Timing
82
Figure 34. Synchronous, Multiplexed Address 16-Bit Single-Word Register Read Timing
83
Figure 35. Synchronous, Multiplexed Address 16-Bit Single-Word Memory Write Timing
84
Figure 36. Synchronous, Multiplexed Address 16-Bit Single-Word Register Write Timing
85
Figure 37. Synchronous, Non-Multiplexed Address, 32-Bit - Sequential Burst Memory Read Transfer Timing
86
Figure 38. Synchronous, Non-Multiplexed Address - 32-Bit Sequential Burst Write Transfer Timing
87
Figure 39. Synchronous, Non-Multiplexed Address 32-Bit - Random Burst Write Transfer Timing
88
Figure 40. Synchronous, Non-Multiplexed Address - 16-Bit Sequential Burst Memory Read Transfer Timing
89
Figure 41. Synchronous, Non-Multiplexed Address - 16-Bit Sequential Burst Write Transfer Timing
90
Figure 42. Synchronous, Non-Multiplexed Address - 16-Bit Random Burst Write Transfer Timing
91
Figure 43. Synchronous, Multiplexed Address - 32-Bit Sequential Burst Memory Read Transfer Timing
92
Figure 44. Synchronous, Multiplexed Address - 32-Bit Sequential Burst Write Transfer Timing
93
Figure 45. Synchronous, Multiplexed Address - 16-Bit Sequential Burst Memory Read Transfer Timing
94
Figure 46. Synchronous, Multiplexed Address - 16-Bit Sequential Burst Write Transfer Timing
95
Figure 47. Timing for Assertion of Cpu_Nstop - Output During Synchronous Burst Write Transfer
96
PCI Interface
97
Table 12. Total-Acextreme® PCI Interface Characteristics
97
Figure 48. Interface between Host PCI Bus and Total-Acextreme® - PCI Signal List
99
Table 13. PCI Bus Interface Signals
100
Table 14. PCI Timing Information
101
Figure 49. PCI Parametric Timing
102
Figure 50. PCI Slave Burst Write
102
Figure 51. PCI Slave Burst Read - PCI Initiator Timing
103
Figure 52. PCI DMA Start Delay
104
Figure 53. PCI DMA Burst Write
104
Figure 54. PCI DMA Burst Read
105
7 Power Inputs
106
Decoupling Capacitors
106
Power Sequencing
106
Figure 55. Recommended +1.8V_PLL Filter Network
106
Figure 56. Power-Up Initialization Sequence Timing
108
8 Mil-Std-1553 Transceiver Options
109
Using the Internal Transceivers
109
Figure 57. Total-Acextreme® Internal Transceiver and Isolation Transformer Connection to MIL-STD-1553 Bus
109
Figure 58. Mandatory Connections for Integrated Transceivers Connection to External Transceivers
110
Using External Fiber Optic Transceivers
111
Figure 59. Total-Acextreme Interface to External Mcair Transceiver
111
Figure 60. Total-Acextreme® Interface to Fiber Optic Transceivers
112
9 Thermal Management for Total-Acextreme
113
10 Register and Memory Addressing
116
10.1 Memory Address Space
116
10.2 Register Address Space
116
11 Total-Acextreme® Signals
117
11.1 Signal Descriptions and Pinout by Functional Groups
117
Table 15. Protocol Configuration
117
Table 16. JTAG Test
118
Table 17. General Purpose Discrete I/O
118
11.2 Host Interface Signals
119
Table 18. PCI Signals
119
Table 19. CPU Data Bus
121
Table 20. RT Address Signals
126
Table 21. Miscellaneous Signals
126
Table 22. Additional Connections & Interface to External Transceiver
129
Table 23. MIL-STD-1553 Interface
131
Table 24. Power and Ground Connections
131
Table 25. no User Connections
132
11.3 Pinout Table
133
Table 26. Signal Pinout by Ball Location
133
11.4 Total-Acextreme® Pin Diagram
137
Figure 61. Total-Acextreme® Pin Diagram
137
12 Mechanical Outline
138
Figure 62. Total-Acextreme® Mechanical Outline Drawing
138
13 Ordering Information
139
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