Asynchronous Interface Mode - DDC Total-AceXtreme MIL-STD-1553 Design Manual

6.2.3 Additional CPU Interface Configuration Options
In addition to the signals listed in Table 3, the Total-AceXtreme includes two
additional static configuration signals, POL_SEL and TRIG_SEL. These signals
operate differently in Asynchronous and Synchronous modes.
In 32-bit mode, POL_SEL is used for selecting the polarity of the RD_nWR input
signal, as follows:
• If POL_SEL = '0', then RD_nWR = '1' to read and '0' to write.
• If POL_SEL = '1', then RD_nWR = '0' to read and '1' to write.
In 16-bit mode, POL_SEL indicates which word is the most significant word, as
follows:
• If POL_SEL is '1' then the value of MSW_nLSW for the least significant word
(15:0) is '1', and the value of MSW_nLSW for the most significant word (31:16) is
'0'.
• If POL_SEL is '0' then the value of MSW_nLSW for the least significant word
(15:0) is '0', and the value of MSW_nLSW for the most significant word (31:16) is
'1'.
In 16-bit Asynchronous mode, TRIG_SEL is used to select which word is transferred
first. If TRIG_SEL = '1', then the upper data word (bits 31:16) is transferred first, and
the lower data word (bits 15:0) is transferred second. If TRIG_SEL = '0', then the
lower data word (bits 15:0) is transferred first, and the upper data word (bits 31:16) is
transferred second.
In 32-bit mode and Synchronous 16-bit mode, TRIG_SEL is not used and must be
connected to logic '1'.
6.3

Asynchronous Interface Mode

In Asynchronous mode, the host processor does not provide a data transfer clock as
an input to the Total-AceXtreme®. In this mode, all transfer timing is controlled by
the Total-AceXtreme's 160 MHz internal clock. This clock is derived from the Total-
AceXtreme's 40 MHz CLK_IN input.
6.3.1.1 Asynchronous 16-bit Mode Options
In Asynchronous 16-bit mode, the order of data transfers for the upper and lower 16-
bit words, along with the polarity of the MSW_nLSW input signal, may be configured
by means of the TRIG_SEL and POL_SEL static input signals, as shown in Table 5.
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