Figure 38. Synchronous, Non-Multiplexed Address - 32-Bit Sequential Burst Write Transfer Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
nSELECT
nDATA_STRB
CPU_ADDR
MEM_nREG
RD_nWR
CPU_WORD_EN[1:0]
CPU_nLAST
CPU_DATA
nDATA_RDY
CPU_nSTOP
Figure 38. Synchronous, Non-Multiplexed Address - 32-bit Sequential Burst Write
Figure 38 Notes:
1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is
asserted (low) and valid address presented initiates the sequential burst
transfer. nSELECT must be asserted low through the full burst cycle. The
nDATA_RDY output is initially asserted low on the clock cycle prior to the
cycle in which the Total-AceXtreme® reads the first data word from the data
bus. CPU_nLAST must be asserted high until the last word is to be written. On
the rising clock edge following CPU_nLAST asserting low, the Total-
AceXtreme reads the last word from the data bus, and nDATA_RDY is de-
asserted (high). At this time (or later) nSELECT must be de-asserted high,
completing the burst write transfer.
2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit data
memory word(s) are to be written. If either or both of these bits is '0', then the
corresponding 16-bit word(s) will not be written. These inputs should be tied
high if unused. For register transfers, the value of CPR_WORD_EN[1:0] must
be '11'.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
Data Device Corporation
www.ddc-web.com
tWait
tCS
tSH
tSS
tAH
tAS
Address
tAH
tAS
tAS
tAS
tLS
tDS tDH
Data Data
tRDD
Transfer Timing
H O S T I N T E R F A C E
Data Data Data Data Data
78
tCH tSHC
tAH
tAH
tLS
tLH tLH
tDH
Data Data
tRDD
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