DDC Total-AceXtreme MIL-STD-1553 Design Manual page 127

Signal Name BALL
nMCRST/nINCMD (O)
DISABLE_BIST (I)
TX_INH_A (I)
TX_INH_B (I)
IRIG_DIG_IN (I)
nINT (O)
CLOCK_IN (I)
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Table 21. Miscellaneous Signals
Pullup/
Pulldown
L12 N/A Mode Code Reset or In-command.
The function of this pin is controlled by bit 19 of "RT_GCFG" (RT Global
Configuration) register.
When RT_GCFG = '0', nMCRST / nINCMD functions as nINCMD.
nINCMD is asserted low to frame the time that a message is being processed
by the Total-AceXtreme.
When RT_GCFG = '1', - nMCRST / nINCMD functions as nMCRST.
In RT mode, nMCRST is asserted low for two CLOCK_IN clock cycles (50 ns)
following receipt of a Reset remote terminal mode command.
In BC-only or Monitor-only modes, this signal is inoperative; i.e., in this case, it
will always output a value of logic '1'.
In addition, nMCRST/nINCMD will also assert low during the time that the
Total-AceXtreme is performing its logic self-test. Therefore, nMCRST/nINCMD
can be monitored to determine when this self-test has been completed.
C13 50k If this input is set to logic '0', the Built-In-Self-Test (BIST) will be enabled after
Pulldown hardware reset (for example, following the low-to-high transition of nPOR
following power-up). A logic '1' input disables both the power-up and user-
initiated automatic BIST.
P13 50k Pullup Transmitter inhibit inputs for Channel A and Channel B, MIL-STD-1553
transmitters. For normal operation, these inputs should be connected to logic
P14 50k Pullup
'0'. To force a shutdown of Channel A and/or Channel B, a value of logic '1'
should be applied to the respective TX_INH input.
N14 50k Pullup Digital IRIG-B time code input supporting 48-bit time-tags.
Digital IRIG data is read once per second.
IRIG Time can be used as the Time-Tag instead of the local timer.
50k Pullup Interrupt Request output.
P2
The operation of nINT is programmable by means of the CPU Interrupt Pin
Control Register. This register is only accessible via the CPU Interface, not the
PCI interface. The user-programmable parameters for nINT include:
(1) Open-drain or TTL output
(2) Active high or low
(3) Pulse or level
(4) For the case of a pulse interrupt, the pulse width is programmable. The
pulse width may be programmed for a value between 3 and 65,537 clock
cycles. The clock used for formulating the nINT pulse width will be the
Total-AceXtreme's internal 160 MHz clock for the Asynchronous CPU
interface mode, and the HOST_CLK for the Synchronous CPU interface
mode.
A8 None 40 MHz clock input (MIL-STD-1553 bus clock)
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Description
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