Table 19. Cpu Data Bus - DDC Total-AceXtreme MIL-STD-1553 Design Manual

Signal Name BALL
C/BE[3]# (I/O)
C/BE[2]# (I/O)
C/BE[1]# (I/O)
C/BE[0]# (I/O)
SERR# (I/O)
INTA# (O)
RST# (I)
11.2.2 FGPI Signals
Signal Name
CPU_DATA(31) (I/O) MSB
CPU_DATA(30) (I/O)
CPU_DATA(29) (I/O)
CPU_DATA(28) (I/O)
CPU_DATA(27) (I/O)
CPU_DATA(26) (I/O)
CPU_DATA(25) (I/O)
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Table 18. PCI Signals
Pullup/
Pulldown
E1 None Bus Command and Byte Enables. These signals are multiplexed on the same
pins. During the address phase of a bus operation, these pins identify the bus
J4 None
command, as shown in the table below. During the data phase of a bus
operation, these pins are used as Byte Enables, with C/BE[0]# enabling byte
K5 None
0 (LSB) and C/BE[3]# enabling byte 3 (MSB). The Total-AceXtreme responds
M3 None
to the following PCI commands
C/BE[3:0]# Description (during address phase)
0 1 1 0 - Memory Read
0 1 1 1 - Memory Write
1 0 1 0 - Configuration Read
1 0 1 1 - Configuration Write
1 1 0 0 - Memory Read Multiple
1 1 1 0 - Memory Read Line
1 1 1 1 - Memory Write and Invalidate
Note that the last three memory commands are aliased to the basic memory
commands: Memory Read and Memory Write.
J2 None System Error. This pin is used for reporting address parity errors, data parity
errors on Special Cycle commands, or any other condition having a
catastrophic system impact.
A9 None Interrupt A. This pin is a level sensitive, active low interrupt to the host
B6 None PCI Reset. Negative true Reset input, normally asserted low following power
turn-on. This input conforms to PCI RST# convention. Asserting RST# low
resets all internal logic, including the PCI interface. However, this signal does
not reset the PLL that generates the internal 160 MHz clock.

Table 19. CPU Data Bus

BAL Pullup/
L Pulldown
A5 None
32-Bit bi-directional CPU Data Bus. This bus interfaces the host processor to
the Total-AceXtreme internal registers and internal RAM. Most of the time, the
A4 None
outputs for DATA31 through DATA00 are in the high impedance state. They
B5 None
drive outward when the host CPU reads the internal RAM or registers.
B4 None
CPU_DATA[31:16] are only used when the 32-bit mode is enabled.
B3 None
D1 None
For the multiplexed address/data mode, CPU_DATA(15:0) operate as the
address bus inputs during the first (address) portion of a transfer cycle.
C2 None
T O T A L - A C E X T R E M E ® S I G N A L S
Description
Description
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