Figure 46. Synchronous, Multiplexed Address - 16-Bit Sequential Burst Write Transfer Timing - DDC Total-AceXtreme MIL-STD-1553 Design Manual

tCLK
HOST_CLK
tCS
nSELECT
nDATA_STRB
tALS
ADDR_LAT
tAS
MEM_nREG
tAS
RD_nWR
tAS
CPU_WORD_EN[1:0]
tLS
CPU_nLAST
tAS
MSW_nLSW
tAS
CPU_DAT Address
A
nDATA_RDY
CPU_nSTOP
Figure 46. Synchronous, Multiplexed Address - 16-bit Sequential Burst Write Transfer
Figure 46 Notes:
1. With nSELECT asserted low and valid address presented on CPU_DATA, a
positive pulse on the ADDR_LAT input satisfying t
Total-AceXtreme® latching the starting address for the sequential burst. One
clock cycle later, a one-clock-cycle wide pulse of nDATA_STRB (low) while
nSELECT remains asserted (low) initiates the sequential burst transfer.
nSELECT must be asserted low through the remainder of the burst cycle. The
nDATA_RDY output is initially asserted low on the clock cycle prior to the
cycle in which the Total-AceXtreme reads the first 16-bit data word from the
data bus. CPU_nLAST must be asserted high until the last 16-bit word is to be
written. On the rising clock edge following CPU_nLAST asserting low, the
Total-AceXtreme reads the last 16-bit word from the data bus, and
nDATA_RDY is de-asserted (high). At this time (or later) nSELECT must be
de-asserted high, completing the burst write transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be '11' through the full
transfer cycle.
3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
Data Device Corporation
www.ddc-web.com
tWait
tSH
tSS
tALH
tAH
tAH
tAH
tDS tDH
Data Data
tRDD
Timing
H O S T I N T E R F A C E
Data Data Data Data Data Data
and T
ALS
86
tCH tSHC
tAH
tAH
tLS
tLH
tAH
tDH
Data Data
tRDD
will result in the
AHL
DS-BU-67301B-G
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