11.3 Pinout Table; Table 26. Signal Pinout By Ball Location - DDC Total-AceXtreme MIL-STD-1553 Design Manual

11.3 Pinout Table

BALL Signal Name
A1 NC
A2 NC
A3 NC
PCI_AD(30)/CPU_DATA(
A4 30)
PCI_AD(31)/CPU_DATA(
A5 31)
PCI_GNT#/CPU_ADDR(1
A6 3)
A7 JTAG_TCK
A8 CLOCK_IN
A9 INTA#
A10 JTAG_TMS
A11 GND_LOGIC
A12 GND_LOGIC
A13 PLL_LOCKED
A14 GND_LOGIC
A15 GND_LOGIC
A16 NC
A17 NC
A18 NC
B1 NC
B2 NC
PCI_AD(27)/CPU_DATA(
B3 27)
PCI_AD(28)/CPU_DATA(
B4 28)
PCI_AD(29)/CPU_DATA(
B5 29)
B6 RST#/nMSTCLR
B7 REQ#/CPU_ADDR(12)
B8 JTAG_TDO
B9 JTAG_nTRST
B10 JTAG_TDI
B11 GND_LOGIC
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Table 26. Signal Pinout by Ball Location

BALL Signal Name
G1 PCI_AD(19)/CPU_DATA(19)
G2 PERR#/CPU_ADDR(11)
G3 PCI_AD(18)/CPU_DATA(18)
G4 GND_LOGIC
G5 GND_LOGIC
G6 GND_LOGIC
G7 GND_LOGIC
G8 GND_LOGIC
G9 GND_LOGIC
G10 RTAD2
G11 RT_AD_LAT
G12 RTAD3
G13 RTAD1
G14 RTAD0
G15 NC
G16 NC
G17 CHA_1553
G18 CHA_1553
H1 PCI_AD(16)/CPU_DATA(16)
H2 STOP#/CPU_ADDR(08)
H3 FRAME#/CPU_ADDR(05)
H4 +3.3V_LOGIC
H5 +3.3V_LOGIC
H6 +3.3V_LOGIC
H7 +3.3V_LOGIC
H8 +3.3V_LOGIC
H9 +3.3V_LOGIC
H10 TXINH_OUT_A
H11 TXINH_IN_A
124
BALL Signal Name
N1 PCI_AD(12)/CPU_DATA(12)
N2 PCI_AD(08)/CPU_DATA(08)
N3 PCI_AD(07)/CPU_DATA(07)
N4 PCI_AD(06)/CPU_DATA(06)
N5 +3.3V_XCVR
N6 +3.3V_XCVR
N7 +3.3V_XCVR
N8 +3.3V_XCVR
N9 +3.3V_XCVR
N10 NC
N11 NC
N12 NC
N13 TAG_ENABLE
N14 IRIG_DIG_IN
N15 NC
N16 NC
N17 CHB_1553 (I/O)
N18 CHB_1553 (I/O)
P1 CPU_nSTOP
P2 nINT
P3 CPU_WORD_EN(0)
P4 CPU_WORD_EN(1)
P5 GND_XCVR
P6 GND_XCVR
P7 GND_XCVR
P8 GND_XCVR
P9 GND_XCVR
P10 NC
P11 GND_XCVR
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