DDC Total-AceXtreme MIL-STD-1553 Design Manual page 51

REF
edge of nDATA_RDY
t nDATA_STRB high delay to nDATA_RDY high
RDD
t CPU_DATA output valid hold time following nDATA_STRB high
OH
t nDATA_STRB high delay to CPU_DATA high-z
OHZ
t CPU_DATA valid setup time prior to nDATA_STRB low
DS
t CPU_DATA valid hold time following nDATA_STRB high
DH
t ADDR_LAT pulse width
ALP
For the 32-bit Asynchronous timing diagrams, POL_SEL is assumed to be connected
to logic '0'. That is, RD_nWR = '1' to read and '0' to write.
For the 16-bit Asynchronous timing diagrams, POL_SEL is assumed to be connected
to logic '0' and TRIG_SEL is assumed to be connected to logic '1'. For these
diagrams, the data indicated as "Data A" is bits 31:16, and is always transferred prior
to the data indicated as "Data B", which is bits 15:0. For the 16-bit Asynchronous
timing diagrams, RD_nWR = '1' to read and '0' to write.
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Table 7. Asynchronous Timing Information
DESCRIPTION
H O S T I N T E R F A C E
NOTES
10pF load
10pF load
10pF load
42
Timing
Characteristics
UNITS
MIN TYP MAX
2 17
2
17
10
0
40
DS-BU-67301B-G
1/14
ns
ns
ns
ns
ns
ns