Processor Registers; Control Registers; Program Counter Format; Program Status Word Format - NEC mPD780208 Subseries User Manual

3.2 Processor Registers

The µ PD780208 Subseries units incorporate the following processor registers.

3.2.1 Control registers

The control registers control the program sequence, statuses, and stack memory. The program counter (PC),
program status word (PSW), and stack pointer (SP) are control registers.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
15
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically reset upon execution of the RETB, RETI, and POP PSW
instructions.
RESET input sets the PSW to 02H.
PSW
(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledgment operations of the CPU.
When IE = 0, the IE flag is set to the interrupt disabled (DI) status. All interrupts except non-maskable
interrupts are disabled.
When IE = 1, the IE flag is set to the interrupt enabled (EI) status and interrupt request acknowledgment
is controlled by an in-service priority flag (ISP), an interrupt mask flag for each interrupt source, and a priority
specification flag.
This flag is reset to (0) upon DI instruction execution or interrupt request acknowledgment and is set to
(1) upon EI instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags used to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction
execution is stored.
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-11. Program Counter Format
PC8
Figure 3-12. Program Status Word Format
7
IE Z RBS1 AC
User's Manual U11302EJ4V0UM
PC7 PC6 PC5 PC4 PC3
0
RBS0 0 ISP CY
0
PC2 PC1 PC0