Format Of Timer Clock Select Register 3 - NEC mPD780208 Subseries User Manual

(1) Timer clock select register 3 (TCL3)
This register sets the serial clock of serial interface channel 1.
TCL3 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL3 to 88H.
Remark Besides setting the serial clock of serial interface channel 1, TCL3 sets the serial clock of serial
interface channel 0.
Symbol 7 6 5
TCL3 TCL37 TCL36 TCL35
Caution
Remarks 1. f
2. Figures in parentheses apply to operation with f
CHAPTER 14 SERIAL INTERFACE CHANNEL 1
Figure 14-2. Format of Timer Clock Select Register 3
4 3 2
TCL34 TCL33 TCL32 TCL31
If TCL3 is to be rewritten with data that is not identical, stop the serial transfer first.
: Main system clock oscillation frequency
X
User's Manual U11302EJ4V0UM
1 0
Address
TCL30 FF43H
TCL33 TCL32
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
Other than above
TCL37 TCL36
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
Other than above
After reset R/W
88H R/W
Serial interface channel 0
TCL31 TCL30
serial clock selection
2
1 0 f /2 (1.25 MHz)
X
3
f /2 (625 kHz)
1 1
X
4
0 0 f /2 (313 kHz)
X
5
0 1 f /2 (156 kHz)
X
6
f /2 (78.1 kHz)
1 0
X
7
1 1 f /2 (39.1 kHz)
X
8
f /2 (19.5 kHz)
0 0
X
9
0 1 f /2 (9.8 kHz)
X
Setting prohibited
Serial interface channel 1
TCL35 TCL34
serial clock selection
2
f /2 (1.25 MHz)
1 0
X
3
1 1 f /2 (625 kHz)
X
4
f /2 (313 kHz)
0 0
X
5
f /2 (156 kHz)
0 1
X
6
1 0 f /2 (78.1 kHz)
X
7
f /2 (39.1 kHz)
1 1
X
8
0 0 f /2 (19.5 kHz)
X
9
0 1 f /2 (9.8 kHz)
X
Setting prohibited
= 5.0 MHz.
X
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