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Instruc- Mnemonic
Operands
tion
Group
16-bit
ADDW
AX, #word
operation
SUBW
AX, #word
CMPW
AX, #word
MULU
X
Multiply/
divide
DIVUW
C
r
Increase/
INC
decrease
saddr
r
DEC
saddr
INCW
rp
DECW
rp
ROR
A, 1
Rotation
ROL
A, 1
RORC
A, 1
ROLC
A, 1
ROR4
[HL]
ROL4
[HL]
ADJBA
BCD
adjust
ADJBS
Bit
MOV1
CY, saddr.bit
manipu-
CY, sfr.bit
lation
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
Remark One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
390
CHAPTER 20 INSTRUCTION SET
Bytes
Clocks
Note 1
Note 2
AX, CY ← AX+word
3
6
–
AX, CY ← AX–word
3
6
–
3
6
–
AX–word
AX ← A × X
2
16
–
AX (Quotient), C (Remainder) ← AX÷C
2
25
–
r ← r+1
1
2
–
(saddr) ← (saddr)+1
2
4
6
r ← r–1
1
2
–
(saddr) ← (saddr)–1
2
4
6
rp ← rp+1
1
4
–
rp ← rp–1
1
4
–
1
2
–
(CY, A
1
2
–
(CY, A
(CY ← A
1
2
–
(CY ← A
1
2
–
A
2
10
12
(HL)
A
2
10
12
(HL)
Decimal Adjust Accumulator after
2
4
–
Addition
Decimal Adjust Accumulator after
2
4
–
Subtract
CY ← (saddr.bit)
3
6
7
CY ← sfr.bit
3
–
7
CY ← A.bit
2
4
–
CY ← PSW.bit
3
–
7
CY ← (HL).bit
2
6
7
(saddr.bit) ← CY
3
6
8
sfr.bit ← CY
3
–
8
A.bit ← CY
2
4
–
PSW.bit ← CY
3
–
8
(HL).bit ← CY
2
6
8
User's Manual U11302EJ4V0UM
Operation
← A
← A
) × 1
, A
7
0
m–1
m
← A
← A
) × 1
, A
0
7
m+1
m
← CY, A
← A
, A
0
7
m–1
← CY, A
← A
, A
7
0
m+1
← (HL)
← A
, (HL)
3–0
3–0
7–4
3–0
← (HL)
3–0
7–4
← (HL)
← A
, (HL)
3–0
7–4
3–0
3–0
← (HL)
7–4
3–0
) selected by the processor clock control
CPU
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
) × 1
×
m
) × 1
×
m
,
,
×
×
×
×
×
×
×
×
×
×
×
×
×
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