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NEC mPD780205 manual available for free PDF download: User Manual
NEC mPD780205 User Manual (418 pages)
8-Bit Single-Chip Microcontrollers
Brand:
NEC
| Category:
Microcontrollers
| Size: 1.75 MB
Table of Contents
10
Table of Contents
24
Chapter 1 Outline
24
Features
25
Applications
25
Ordering Information
25
Quality Grade
26
Pin Configuration (Top View)
29
Series Lineup
31
Block Diagram
32
Overview of Functions
33
Mask Options
33
Mask Options in Mask ROM Versions
34
Chapter 2 Pin Functions
34
Pin Function List
34
Normal Operating Mode Pins
37
PROM Programming Mode Pins ( Μ PD78P0208 Only)
38
Description of Pin Functions
38
P00 to P04 (Port 0)
38
P10 to P17 (Port 1)
39
P20 to P27 (Port 2)
39
P30 to P37 (Port 3)
40
P70 to P74 (Port 7)
40
P80 to P87 (Port 8)
40
P90 to P97 (Port 9)
41
P100 to P107 (Port 10)
41
P110 to P117 (Port 11)
41
P120 to P127 (Port 12)
41
FIP0 to FIP12
42
Vload
42
Av Ref
42
Av DD
42
Av Ss
42
Reset
42
X1 and X2
43
Pin I/O Circuits and Recommended Connection of Unused Pins
43
Types of Pin I/O Circuits
45
Pin I/O Circuits
48
Chapter 3 Cpu Architecture
48
Memory Space
48
Memory Map ( Μ PD780204 and Μ PD780204A)
49
Memory Map ( Μ PD780205 and Μ PD780205A)
50
Memory Map ( Μ PD780206)
51
Memory Map ( Μ PD780208)
52
Memory Map ( Μ PD78P0208)
53
Internal Program Memory Space
53
Internal ROM Capacity
53
Vector Table
54
Internal Data Memory Space
54
Special-Function Register (SFR) Area
55
Data Memory Addressing
55
Data Memory Addressing ( Μ PD780204 and Μ PD780204A)
56
Data Memory Addressing ( Μ PD780205 and Μ PD780205A)
57
Data Memory Addressing ( Μ PD780206)
58
Data Memory Addressing ( Μ PD780208)
59
Data Memory Addressing ( Μ PD78P0208)
60
Processor Registers
60
Control Registers
60
Program Counter Format
60
Program Status Word Format
61
Stack Pointer Format
62
Data to Be Saved to Stack Memory
62
Data to Be Reset From Stack Memory
63
General-Purpose Registers
63
General-Purpose Register Configuration
64
Special-Function Registers (Sfrs)
65
Special-Function Register List
68
Instruction Address Addressing
68
Relative Addressing
69
Immediate Addressing
70
Table Indirect Addressing
71
Register Addressing
72
Operand Address Addressing
72
Implied Addressing
73
Register Addressing
74
Direct Addressing
75
Short Direct Addressing
76
Special-Function Register (SFR) Addressing
77
Register Indirect Addressing
78
Based Addressing
79
Based Indexed Addressing
79
Stack Addressing
80
Chapter 4 Port Functions
80
Port Functions
80
Port Types
81
Port Functions
83
Port Configuration
83
Port 0
84
Block Diagram of P00 and P04
84
Block Diagram of P01 to P03
85
Port 1
85
Block Diagram of P10 to P17
86
Port 2
86
Block Diagram of P20, P21, P23 to P26
87
Block Diagram of P22 and P27
88
Port 3
88
Block Diagram of P30 to P37
89
Port 7
89
Block Diagram of P70 to P74
90
Port 8
90
Block Diagram of P80 to P87
91
Port 9
91
Block Diagram of P90 to P97
92
Port 10
92
Block Diagram of P100 to P107
93
Port 11
93
Block Diagram of P110 to P117
94
Port 12
94
Block Diagram of P120 to P127
95
Port Function Control Registers
95
Port Mode Register and Output Latch Setting When Alternate Function Is Used
96
Format of Port Mode Register
97
Format of Pull-Up Resistor Option Register
98
Port Function Operations
98
Writing to I/O Port
98
Reading From I/O Port
98
Operations On I/O Port
99
Selection of Mask Option
99
Comparison Between Mask Option of Mask ROM Version and Μ PD78P0208
100
Chapter 5 Clock Generator
100
Clock Generator Functions
100
Clock Generator Configuration
101
Clock Generater Block Diagram
102
Clock Generator Control Registers
102
Feedback Resistor of Subsystem Clock
103
Format of Processor Clock Control Register
104
Relationship Between CPU Clock and Minimum Instruction Execution Time
105
Format of Display Mode Register 0
108
Format of Display Mode Register 1
109
System Clock Oscillator
109
Main System Clock Oscillator
109
External Circuit of Main System Clock Oscillator
110
Subsystem Clock Oscillator
110
External Circuit of Subsystem Clock Oscillator
111
Examples of Incorrect Resonator Connection
113
Divider
113
When Subsystem Clock Is Not Used
114
Clock Generator Operations
115
Main System Clock Operations
115
Main System Clock Stop Function
116
Subsystem Clock Operations
117
Changing System Clock and CPU Clock Settings
117
Time Required for Switchover Between System Clock and CPU Clock
117
Maximum Time Required for CPU Clock Switchover
118
System Clock and CPU Clock Switching Procedure
118
System Clock and CPU Clock Switching
119
Chapter 6 16-Bit Timer/Event Counter
119
Outline of Timers Incorporated in Μ PD780208 Subseries
120
16-Bit Timer/Event Counter Functions
120
Timer/Event Counter Operations
121
16-Bit Timer/Event Counter Interval Time
121
16-Bit Timer/Event Counter Square-Wave Output Ranges
122
16-Bit Timer/Event Counter Configuration
127
16-Bit Timer/Event Counter Control Registers
128
Format of Timer Clock Select Register 0
130
Format of 16-Bit Timer Mode Control Register
131
Format of 16-Bit Timer Output Control Register
132
Format of Port Mode Register 3
133
Format of External Interrupt Mode Register
134
Format of Sampling Clock Select Register
135
16-Bit Timer/Event Counter Operations
135
Interval Timer Operations
136
16-Bit Timer/Event Counter Interval Time
136
Interval Timer Operation Timing
137
PWM Output Operations
138
Pulse Width Measurement Operations
139
Configuration Diagram for Pulse Width Measurement in Free-Running Mode
140
External Event Counter Operation
141
External Event Counter Configuration Diagram
142
Square-Wave Output Operation
142
16-Bit Timer/Event Counter Square-Wave Output Ranges
143
16-Bit Timer/Event Counter Operating Precautions
144
Capture Register Data Retention Timing
145
Chapter 7 8-Bit Timer/Event Counter
145
8-Bit Timer/Event Counter Functions
145
8-Bit Timer/Event Counter Mode
146
8-Bit Timer/Event Counter Interval Time
147
8-Bit Timer/Event Counter Square-Wave Output Ranges
148
16-Bit Timer/Event Counter Mode
148
Interval Time When 8-Bit Timer/Event Counter Is Used As 16-Bit Timer/Event Counter
149
Is Used As 16-Bit Timer/Event Counter
150
8-Bit Timer/Event Counter Configuration
152
Block Diagram of 8-Bit Timer/Event Counter Output Controller 1
153
8-Bit Timer/Event Counter Control Registers
154
Format of Timer Clock Select Register 1
155
Format of 8-Bit Timer Mode Control Register
156
Format of 8-Bit Timer Output Control Register
157
Format of Port Mode Register 3
158
8-Bit Timer/Event Counter Operations
158
8-Bit Timer/Event Counter Mode
159
8-Bit Timer/Event Counter 1 Interval Time
159
8-Bit Timer/Event Counter 2 Interval Time
160
External Event Counter Operation Timing (With Rising Edge Specified)
161
8-Bit Timer/Event Counter Square-Wave Output Ranges
161
Square-Wave Output Operation Timing
162
16-Bit Timer/Event Counter Mode
163
(TM1 and TM2) Is Used As 16-Bit Timer/Event Counter
164
External Event Counter Operation Timing (With Rising Edge Specified)
165
(TM1 and TM2) Are Used As 16-Bit Timer/Event Counter
165
Square-Wave Output Operation Timing
166
8-Bit Timer/Event Counter Operating Precautions
167
Timing After Compare Register Change During Timer Count Operation
168
Chapter 8 Watch Timer
168
Watch Timer Functions
168
Interval Timer Interval Time
169
Watch Timer Configuration
169
Watch Timer Control Registers
171
Format of Timer Clock Select Register 2
172
Format of Watch Timer Mode Control Register
173
Watch Timer Operations
173
Watch Timer Operation
173
Interval Timer Operation
173
Interval Timer Interval Time
174
Chapter 9 Watchdog Timer
174
Watchdog Timer Functions
174
Watchdog Timer Program Loop Detection Time
174
Interval Time
175
Watchdog Timer Configuration
177
Watchdog Timer Control Registers
178
Format of Timer Clock Select Register 2
179
Format of Watchdog Timer Mode Register
180
Watchdog Timer Operations
180
Watchdog Timer Operation
180
Watchdog Timer Program Loop Detection Time
181
Interval Timer Operation
182
Chapter 10 Clock Output Controller
182
Clock Output Controller Functions
183
Clock Output Controller Configuration
183
Clock Output Function Control Registers
184
Format of Timer Clock Select Register 0
185
Format of Port Mode Register 3
186
Chapter 11 Buzzer Output Controller
186
Buzzer Output Controller Functions
186
Buzzer Output Controller Configuration
187
Buzzer Output Function Control Registers
188
Format of Timer Clock Select Register 2
189
Format of Port Mode Register 3
190
Chapter 12 A/D Converter
190
A/D Converter Functions
190
A/D Converter Configuration
191
A/D Converter Block Diagram
194
A/D Converter Control Registers
195
Format of A/D Converter Mode Register
196
Format of A/D Converter Input Select Register
197
A/D Converter Operations
197
Basic Operations of A/D Converter
198
Basic Operation of A/D Converter
199
Input Voltage and Conversion Results
200
A/D Converter Operating Mode
201
A/D Conversion By Software Start
202
A/D Converter Precautions
203
Analog Input Pin Processing
204
A/D Conversion End Interrupt Request Generation Timing
205
Chapter 13 Serial Interface Channel 0
206
Functions of Serial Interface Channel 0
207
Configuration of Serial Interface Channel 0
211
Control Registers of Serial Interface Channel 0
212
Format of Timer Clock Select Register 3
213
Format of Serial Operating Mode Register 0
214
Format of Serial Bus Interface Control Register
216
Format of Interrupt Timing Specification Register
217
Operations of Serial Interface Channel 0
217
Operation Stop Mode
218
3-Wire Serial I/O Mode Operation
221
Wire Serial I/O Mode Timing
222
RELT and CMDT Operations
223
SBI Mode Operation
224
Example of Serial Bus Configuration with SBI
226
SBI Transfer Timing
227
Bus Release Signal
228
Address
229
Commands
230
Acknowledge Signal
231
BUSY and READY Signals
236
RELT, CMDT, RELD, and CMDD Operations (Master)
237
ACKT Operation
238
ACKE Operations
239
ACKD Operations
242
Pin Configuration
249
2-Wire Serial I/O Mode Operation
253
Wire Serial I/O Mode Timing
254
RELT and CMDT Operations
255
SCK0/P27 Pin Output Manipulation
256
Chapter 14 Serial Interface Channel 1
256
Functions of Serial Interface Channel 1
257
Configuration of Serial Interface Channel 1
260
Control Registers of Serial Interface Channel 1
261
Format of Timer Clock Select Register 3
262
Format of Serial Operating Mode Register 1
264
Format of Automatic Data Transmit/Receive Control Register
265
Format of Automatic Data Transmit/Receive Interval Specification Register
268
Operations of Serial Interface Channel 1
268
Operation Stop Mode
269
3-Wire Serial I/O Mode Operation
270
Wire Serial I/O Mode Timing
271
Circuit for Switching Transfer Bit Order
272
3-Wire Serial I/O Mode Operation with Automatic Transmit/Receive Function
279
Basic Transmission/Reception Mode Operation Timing
280
Basic Transmission/Reception Mode Flowchart
283
Basic Transmission Mode Operation Timing
284
Basic Transmission Mode Flowchart
285
Buffer RAM Operation in 6-Byte Transmission (In Basic Transmission Mode)
287
Repeat Transmission Mode Operation Timing
288
Repeat Transmission Mode Flowchart
289
Buffer RAM Operation in 6-Byte Transmission (In Repeat Transmission Mode)
291
Automatic Transmission/Reception Suspension and Restart
292
System Configuration with Busy Control Option
293
Operation Timing When Using Busy Control Option (BUSY0 = 0)
294
Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0)
295
Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1)
296
Automatic Transmit/Receive Interval
297
Interval Determined By CPU Processing (With Internal Clock Operation)
298
Interval Determined By CPU Processing (With External Clock Operation)
299
Chapter 15 Vfd Controller/Driver
299
VFD Controller/Driver Functions
300
VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0)
301
VFD Controller/Driver Configuration
303
VFD Controller/Driver Control Registers
303
Control Registers
305
Format of Display Mode Register 0
307
Format of Display Mode Register 1
308
Format of Display Mode Register 2
310
One-Display Period and Cut Width
311
Selecting Display Mode
312
Display Mode and Display Output
313
Display Data Memory
314
Key Scan Flag and Key Scan Data
314
Key Scan Flag
314
Key Scan Data
315
Light Leakage of VFD
317
Display Examples
318
Segment Type (Display Mode 1: DSPM05 = 0)
320
Dot Type (Display Mode 1: DSPM05 = 0)
321
Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment X 16-Digit Display Mode
322
Display Type in Which a Segment Spans Two or More Grids (Display Mode 2: DSPM05 = 1)
322
Display Data Memory Configuration and Data Reading Order (Display Mode 2)
324
Grid Driving Timing
326
Calculating Total Power Dissipation
326
Segment Type (Display Mode 1: DSPM05 = 0)
328
Relationship Between Display Data Memory Contents and Segment Outputs in 10-Segment X 11-Digit Display Mode
329
Dot Type (Display Mode 1: DSPM05 = 0)
331
Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment X 16-Digit Display Mode
332
Display Type in Which a Segment Spans Two or More Grids (Display Mode 2: DSPM05 = 1)
333
Grid Driving Timing
335
Chapter 16 Interrupt and Test Functions
335
Interrupt Function Types
336
Interrupt Sources and Configuration
337
Basic Configuration of Interrupt Function
339
Interrupt Function Control Registers
340
Format of Interrupt Request Flag Register
341
Format of Interrupt Mask Flag Register
342
Format of Priority Specification Flag Register
343
Format of External Interrupt Mode Register
344
Format of Sampling Clock Select Register
345
Noise Eliminator I/O Timing (When Rising Edge Is Detected)
346
Format of Program Status Word
347
Interrupt Servicing Operations
347
Non-Maskable Interrupt Request Acknowledgment Operation
348
Non-Maskable Interrupt Request Acknowledgment Flowchart
349
Non-Maskable Interrupt Request Acknowledgment Operation
350
Maskable Interrupt Request Acknowledgment Operation
351
Interrupt Request Acknowledge Processing Algorithm
352
Software Interrupt Request Acknowledgment Operation
353
Multiple Interrupt Servicing
354
Multiple Interrupt Servicing Example
356
Interrupt Request Hold
357
Test Functions
357
Test Function Control Registers
358
Test Input Signal Acknowledgment Operation
359
Chapter 17 Standby Function
359
Standby Function and Configuration
359
Standby Function
360
Standby Function Control Register
361
Standby Function Operations
361
HALT Mode
362
HALT Mode Release By Interrupt Request Generation
363
HALT Mode Release By RESET Input
364
STOP Mode
365
STOP Mode Release By Interrupt Request Generation
366
STOP Mode Release By RESET Input
367
Chapter 18 Reset Function
367
Reset Function
368
Timing of Reset By RESET Input
369
Hardware Status After Reset
371
CHAPTER 19 Μ PD78P0208
372
Internal Memory Size Switching Register
373
Format of Internal Memory Size Switching Register (IMS)
374
Internal Expansion RAM Size Switching Register
375
PROM Programming
375
Operating Modes
377
PROM Write Procedure
378
Page Program Mode Timing
379
Byte Program Mode Flowchart
380
Byte Program Mode Timing
381
PROM Read Procedure
382
Screening of One-Time PROM Version
383
Chapter 20 Instruction Set
384
Conventions
384
Operand Identifiers and Description Methods
385
Description of "Operation" Column
385
Description of "Flag Operation" Column
386
Operation List
394
Instructions Listed By Addressing Type
398
APPENDIX A DIFFERENCES BETWEEN Μ PD78044H, 780228, and 780208 SUBSERIES
399
Appendix Bdevelopment Tools
400
B-1 Configuration of Development Tools
401
B.1 Software Package
401
Language Processing Software
401
Software Package
402
B.3 Control Software
402
Control Software
403
PROM Programming Tools
403
Hardware
403
Software
404
Debugging Tools (Hardware)
404
When Using In-Circuit Emulator IE-78K0-NS, IE-78K0-NS-A
405
When Using In-Circuit Emulator IE-78001-R-A
406
Debugging Tools (Software)
407
B.7 Embedded Software
407
Embedded Software
408
Method for Upgrading From Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
409
Conversion Socket (EV-9200GF-100) Package Drawing and Recommended Footprint
410
B-3 Recommended Footprint for EV-9200GF-100 (For Reference Purposes Only)
411
Notes On Target System Design
412
B-5 Connection Conditions of Target System (When NP-100GF-TQ Is Used)
413
Appendix Cregister Index
413
Register Index (By Register Name)
415
Register Index (By Register Symbol)
417
Appendix D Revision History
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