Table of Contents
Advertisement
(c) Interrupt timing specification register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
Symbol
7
<6>
<5>
SINT
0
CLD
SIC SVAM
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bits 0 to 3 to 0.
Remark
SVA:
CSIIF0: Interrupt request flag for INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
252
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
<4>
3
2
1
0
0
0
R/W
R/W
Slave address register
User's Manual U11302EJ4V0UM
0
Address
After reset
0
FF63H
00H
SVAM
SVA bit to be used as slave address
0
Bits 0 to 7
1
Bits 1 to 7
SIC
INTCSI0 interrupt source selection
CSIIF0 is set upon termination of serial interface
0
channel 0 transfer
CSIIF0 is set upon bus release detection or
1
termination of serial interface channel 0 transfer
R
Note 2
CLD
SCK0 pin level
0
Low level
1
High level
R/W
Note 1
R/W
Advertisement
Table of Contents
