Interval Determined By Cpu Processing (With Internal Clock Operation) - NEC mPD780208 Subseries User Manual

(a) When automatic transmit/receive function is performed using an internal clock
The internal clock operation is selected when bit 1 (CSIM11) of serial operating mode register 1
(CSIM1) is set to 1.
In this case, the interval is determined as follows by CPU processing.
When bit 7 (ADTI7) of the automatic data transmit/receive interval specification register (ADTI) is set
to 0, the interval is determined by CPU processing. When ADTI7 is set to 1, the interval is determined
by the contents of ADTI or by CPU processing, whichever is greater.
For the interval determined by ADTI, see Figure 14-5 Format of Automatic Data Transmit/Receive
Interval Specification Register.
Table 14-3. Interval Determined by CPU Processing (with Internal Clock Operation)
When using multiplication instruction
When using division instruction
External access 1-wait mode
Other than above
T :
SCK
f :
SCK
T :
CPU
f :
CPU
MAX. (a, b) : a or b, whichever is greater
Figure 14-24. Operation Timing When Automatic Transmit/Receive
f
X
T
CPU
f
CPU
(n = 1)
T
SCK
SCK1
SO1 D7
SI1 D7
f : Main system clock oscillation frequency
X
f : CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC))
CPU
T : 1/f
CPU CPU
T : 1/f
SCK SCK
f : Serial clock frequency
SCK
CHAPTER 14 SERIAL INTERFACE CHANNEL 1
CPU Processing
1/f
SCK
Serial clock frequency
1/f
CPU
CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the
processor clock control register (PCC))
Function Is Operating with Internal Clock
D6 D5 D4
D6 D5 D4
User's Manual U11302EJ4V0UM
Interval
MAX. (2.5T , 13T )
SCK CPU
MAX. (2.5T , 20T )
SCK CPU
MAX. (2.5T , 9T )
SCK CPU
MAX. (2.5T , 7T )
SCK CPU
D3 D2 D1
D3 D2 D1
Interval
D0
D0
297