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Symbol
7
6
5
DSPM0
KSF
DSPM06 DSPM05 SEGS4 SEGS3 SEGS2
R/W DSPM05 Display mode setting
0
Display mode 1 (segment/character type)
1
Display mode 2 (type in which a segment spans two or more grids)
R/W DSPM06 Mode of noise eliminator for subsystem clock
0
2.5 MHz < f
1.25 MHz ≤ f
1
R
KSF
Timing status
0
Display timing
1
Key scan timing
Notes 1. Bit 7 (KSF) is a read-only bit.
2. Set this bit according to the main system clock oscillation frequency (f
eliminator operates during VFD display.
3. When f
X
Caution When the main system clock frequency selected is below 1.25 MHz and the VFD controller/
driver is enabled, make sure to use the main system clock for watch timer counting by
setting TCL24 to 0.
106
CHAPTER 5 CLOCK GENERATOR
Figure 5-4. Format of Display Mode Register 0 (2/2)
4
3
2
1
SEGS1 SEGS0
≤ 5.0 MHz
X
≤ 2.5 MHz
Note 3
X
is used between 1.25 MHz and 2.5 MHz, set bit 6 (DSPM06) to 1 prior to VFD display.
User's Manual U11302EJ4V0UM
0
Address
After reset
F F A 0 H
0 0 H
Note 2
R/W
Note 1
R/W
) selected. The noise
X
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