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(2) External event counter operations
The external event counter counts the number of external clock pulses input to the TI1/P33 pin by using
the two channels of 8-bit timer registers 1 and 2 (TM1 and TM2).
TM1 is incremented each time the valid edge specified by timer clock select register 1 (TCL1) is input. If
TM1 overflows as a result, the overflow signal is used as the count clock, and TM2 is incremented. Either
the rising or falling edge can be selected.
When the count value of TM1 and TM2 matches the value of the 8-bit compare registers (CR10 and CR20),
both TM1 and TM2 are cleared to 0 and the interrupt request signal (INTTM2) is generated.
Figure 7-12. External Event Counter Operation Timing (with Rising Edge Specified)
TI1 pin input
TMS (TM1, TM2) count value
CR10, CR20
INTTM2
Caution Even in the 16-bit timer/event counter mode, an interrupt request (INTTM1) will be generated when
the TM1 count value matches the CR10 value, inverting the flip-flop of 8-bit timer/event counter
output controller 1. Thus, when using the 8-bit timer/event counters as a 16-bit interval timer, set
the mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.
When reading the 16-bit timer register (TMS) count value, use a 16-bit memory manipulation
instruction.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER
0000 0001
0002 0003 0004 0005
User's Manual U11302EJ4V0UM
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0000 0001 0002 0003
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