Format Of External Interrupt Mode Register - NEC mPD780208 Subseries User Manual

(4) External interrupt mode register (INTM0)
This register sets the valid edge for INTP0 to INTP2 and TI0.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 to 00H.
Remarks 1. INTP0 is also used for TI0/P00.
2. INTP3 is fixed to the falling edge.
Symbol
7 6 5
INTM0 ES31 ES30 ES21 ES20 ES11 ES10
Caution When using the INTP0/TI0/P00 pin as a timer input pin (TI0), stop the operation of the 16-bit timer
by clearing bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) to 0,
0, 0, before setting the valid edge of TI0. When using the INTP0/TI0/P00 pin as an external
interrupt input pin (INTP0), the valid edge of INTP0 may be set while the 16-bit timer is operating.
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
Figure 16-5. Format of External Interrupt Mode Register
4 3 2 1
0
User's Manual U11302EJ4V0UM
0 Address After reset
0 FFECH 00H
ES11 ES10 INTP0/TI0 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
ES21 ES20 INTP1 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
ES31 ES30 INTP2 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
R/W
R/W
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