NEC mPD780208 Subseries User Manual page 234

R/W ACKE Acknowledge signal output control
0 Acknowledge signal automatic output disabled (output with ACKT enabled)
Before completion
of transfer
1 After completion
of transfer
R ACKD Acknowledge detection
Clear conditions (ACKD = 0)
• At the falling edge of SCK0 immediately after the
busy mode has been released when a transfer start
instruction is executed
• When CSIE0 = 0
• When RESET input is applied
R/W BSYE Note Synchronizing busy signal output control
Busy signal which is output in synchronization with the falling edge of SCK0 clock just after
0
execution of the instruction to be cleared to 0 (sets ready state) is disabled.
1 Busy signal is output at the falling edge of SCK0 clock following the acknowledge signal.
Note Busy mode can be cleared by start of serial interface transfer. However, the BSYE flag is not
cleared to 0.
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
234
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
The acknowledge signal is output in synchronization with the 9th clock
falling edge of SCK0 (automatically output when ACKE = 1).
The acknowledge signal is output in synchronization with the falling edge of SCK0
just after execution of the instruction to be set to 1 (automatically output when
ACKE = 1). However, ACKE is not automatically cleared to 0 after
acknowledge signal output.
User's Manual U11302EJ4V0UM
Set conditions (ACKD = 1)
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of
transfer
(continued)