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1.7 Block Diagram
TO0/P30
16-bit timer/
TI0/P00
event counter
TO1/P31
8-bit timer/
event counter 1
TI1/P33
TO2/P32
8-bit timer/
TI2/P34
event counter 2
Watchdog timer
Watch timer
SI0/SB0/P25
Serial
SO0/SB1/P26
interface 0
SCK0/P27
SI1/P20
SO1/P21
Serial
SCK1/P22
interface 1
STB/P23
BUSY/P24
ANI0/P10 to
ANI7/P17
AV
A/D converter
DD
AV
SS
AV
REF
INTP0/P00 to
Interrupt control
INTP3/P03
BUZ/P36
Buzzer output
Clock output
PCL/P35
control
Remarks 1. The internal ROM and RAM capacities vary depending on the product.
2. Pin names in parentheses only apply to the µ PD78P0208.
CHAPTER 1 OUTLINE
78K/0
ROM
CPU core
RAM
V
V
IC
DD
SS
(V
)
PP
User's Manual U11302EJ4V0UM
P00
Port 0
P01 to P03
P04
Port 1
P10 to P17
Port 2
P20 to P27
Port 3
P30 to P37
Port 7
P70 to P74
Port 8
P80 to P87
Port 9
P90 to P97
Port 10
P100 to P107
Port 11
P110 to P117
Port 12
P120 to P127
FIP0 to FIP52
VFD
controller/
driver
V
LOAD
RESET
X1
System
X2
control
XT1/P04
XT2
31
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