Format Of Serial Operating Mode Register 0 - NEC mPD780208 Subseries User Manual

Figure 13-3. Format of Serial Operating Mode Register 0
Symbol <7> <6> <5> 4
CSIM CSIM
CSIM0
CSIE0 COI WUP
04
R/W CSIM CSIM
Serial interface channel 0 clock selection
01 00
0 x Input clock to SCK0 pin from off-chip
1 0 8-bit timer register 2 (TM2) output
1 1 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W CSIM CSIM CSIM
PM25 P25 PM26 P26 PM27 P27
04 03 02
0
×
0 1
1
Note 3 Note 3
×
0
1 0
1 0
Note 3 Note 3
×
0
1 1
1 0
R/W WUP Wakeup function control
0 Interrupt request signal generation with each serial transfer in any mode
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the
1
slave address register (SVA) in SBI mode
R COI Slave address comparison result flag
0 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data
1 Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W CSIE0 Serial interface channel 0 operation control
0 Operation stopped
1 Operation enabled
Notes 1. Bit 6 (COI) is a read-only bit.
2. Can be used as P25 (CMOS input) when used only for transmission.
3. Can be used freely as port function.
4. To use the wakeup function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification
register (SINT) to 0.
5. COI becomes 0 when CSIE0 = 0.
Remark ×:
PM××: Port mode register
P××:
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
3 2 1 0
Address
CSIM CSIM CSIM
FF60H
03 02 01 00
Operating
mode
3-wire serial
×
0 0 0 1
I/O mode
SBI mode
×
0 0 0 1
Note 3 Note 3
× ×
0 0 1
2-wire serial
×
0 0 0 1 I/O mode
Note 3 Note 3
× ×
0 0 1
Note 4
Note 5
don't care
Port output latch
User's Manual U11302EJ4V0UM
After reset R/W
Note 1
00H R/W
Start SI0/P25
bit pin function
MSB Note 2
SI0
(input)
LSB
MSB P25
(CMOS I/O)
SB0
(N-ch open-drain
I/O)
MSB P25
(CMOS I/O)
SB0
(N-ch open-drain
I/O)
SO0/P26 SCK0/P27
pin function pin function
SCK0
SO0
(CMOS I/O)
(CMOS output)
SB1 SCK0
(N-ch open-drain (CMOS I/O)
I/O)
P26
(CMOS I/O)
SB1 SCK0
(N-ch open-drain (N-ch open-drain
I/O) I/O)
P26
(CMOS I/O)
213