Table of Contents
Advertisement
18.1 Reset Function
The following two operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at
addresses 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each
hardware is set to the status as shown in Table 18-1. Each pin is high impedance during reset input or during
the oscillation stabilization time just after reset release.
When a high level is input to the RESET pin, the reset is released and program execution starts after the lapse
of the oscillation stabilization time (2
released after the reset and program execution starts after the lapse of the oscillation stabilization time (2
(see Figures 18-2 to 18-4).
Cautions 1. For an external reset, input a low level to the RESET pin for 10 µ s or more.
2. During reset input, main system clock oscillation remains stopped but subsystem clock
oscillation continues.
3. When the STOP mode is released by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
RESET
Count clock
CHAPTER 18 RESET FUNCTION
17
/f
). The reset applied by watchdog timer overflow is automatically
X
Figure 18-1. Block Diagram of Reset Function
User's Manual U11302EJ4V0UM
Reset controller
Overflow
Watchdog timer
Stop
17
/f
)
X
Reset
signal
Interrupt
function
367
Advertisement
Table of Contents
