Maskable Interrupt Request Acknowledgment Operation - NEC mPD780208 Subseries User Manual

16.4.2 Maskable interrupt request acknowledgment operation

A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask
(MK) flag of the interrupt request is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled
state (with IE flag set to 1). However, a low-priority interrupt is not acknowledged during high-priority interrupt request
servicing (with ISP flag reset to 0).
Table 16-3 shows the time required until interrupt servicing is executed after a maskable interrupt request has been
generated.
For the interrupt request acknowledgment timing, refer to Figures 16-13 and 16-14.
Table 16-3. Times from Maskable Interrupt Request Generation to Interrupt Servicing
When ××PR = 0
When ××PR = 1
Note If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark 1 clock cycle = 1/f
If two or more maskable interrupt requests are generated simultaneously, the request specified as higher priority
by the priority specification flag is acknowledged first. If the same priority is specified by the priority specification flag,
the interrupt with the highest default priority is acknowledged first.
Any pending interrupt requests are acknowledged when they become acknowledgeable.
Figure 16-12 shows interrupt request acknowledgment algorithms.
If a maskable interrupt request is acknowledged, the contents of the program status word (PSW) and program
counter (PC) are saved in the stacks in that order. Then, the IE flag is reset to 0, and the acknowledged interrupt
request priority specification flag contents are transferred to the ISP flag. Further, the vector table data determined
for each interrupt request is loaded into the PC and branched.
Return from the interrupt is possible with the RETI instruction.
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CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
Minimum Time
7 clock cycles
8 clock cycles
(f : CPU clock)
CPU CPU
User's Manual U11302EJ4V0UM
Note
Maximum Time
32 clock cycles
33 clock cycles