NEC mPD780208 Subseries User Manual page 387

Instruc- Mnemonic Operands
tion
Group
MOVW rp, #word
16-bit
data
saddrp, #word
transfer
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
AX, !addr16
!addr16, AX
XCHW AX, rp
8-bit
ADD A, #byte
operation
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
ADDC A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
3. Only when rp = BC, DE, or HL
4. Except r = A
Remark One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
CHAPTER 20 INSTRUCTION SET
Bytes
Clocks
Note 1 Note 2
3 6
4 8 10
4 – 10
2 6
2 6
2 –
2 –
Note 3
1 4
Note 3
1 4
3 10 12
3 10 12
Note 3
1 4
2 4
3 6
Note 4
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 4
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
User's Manual U11302EJ4V0UM
Operation
rp ← word
–
(saddrp) ← word
sfrp ← word
AX ← (saddrp)
8
(saddrp) ← AX
8
AX ← sfrp
8
sfrp ← AX
8
AX ← rp
–
rp ← AX
–
AX ← (addr16)
(addr16) ← AX
AX ↔ rp
–
A, CY ← A+byte
–
(saddr), CY ← (saddr)+byte
8
A, CY ← A+r
–
r, CY ← r+A
–
A, CY ← A+(saddr)
5
A, CY ← A+(addr16)
9
A, CY ← A+(HL)
5
A, CY ← A+(HL+byte)
9
A, CY ← A+(HL+B)
9
A, CY ← A+(HL+C)
9
A, CY ← A+byte+CY
–
(saddr), CY ← (saddr)+byte+CY
8
A, CY ← A+r+CY
–
r, CY ← r+A+CY
–
A, CY ← A+(saddr)+CY
5
A, CY ← A+(addr16)+CY
9
A, CY ← A+(HL)+CY
5
A, CY ← A+(HL+byte)+CY
9
A, CY ← A+(HL+B)+CY
9
A, CY ← A+(HL+C)+CY
9
) selected by the processor clock control
CPU
Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
387