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(4) Interrupt timing specification register (SINT)
This register sets the bus release interrupt and address mask functions and displays the SCK0 pin level
status.
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
Figure 13-5. Format of Interrupt Timing Specification Register
Symbol
7
<6>
<5>
SINT
0
CLD
SIC SVAM
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When using wakeup function, set SIC to 0.
3. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bits 0 to 3 to 0.
Remark
SVA:
CSIIF0: Interrupt request flag for INTCSI0
CSIE0:
216
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
<4>
3
2
1
0
0
0
Slave address register
Bit 7 of serial operating mode register 0 (CSIM0)
User's Manual U11302EJ4V0UM
0
Address
After reset
0
FF63H
00H
R/W
SVAM
SVA bit to be used as slave address
0
Bits 0 to 7
1
Bits 1 to 7
R/W
SIC
INTCSI0 interrupt source selection
CSIIF0 is set upon termination of serial interface
0
channel 0 transfer
CSIIF0 is set upon bus release detection or
1
termination of serial interface channel 0 transfer
R
CLD
SCK0 pin level
0
Low level
1
High level
R/W
Note 1
R/W
Note 2
Note 3
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