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NEC mPD17120 Subseries User Manual

4-bit single-chip microcontroller
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µ PD17120 SUBSERIES
4-BIT SINGLE-CHIP MICROCONTROLLER
©
1993
µ PD17120
µ PD17121
µ PD17132
µ PD17133
µ PD17P132
µ PD17P133
Document No. IEU-1367A
(O. D. No. IEU-835A)
Date Published July 1995 P
Printed in Japan

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Summary of Contents for NEC mPD17120 Subseries

  • Page 1 µ PD17120 SUBSERIES 4-BIT SINGLE-CHIP MICROCONTROLLER µ PD17120 µ PD17121 µ PD17132 µ PD17133 µ PD17P132 µ PD17P133 Document No. IEU-1367A (O. D. No. IEU-835A) Date Published July 1995 P Printed in Japan © 1993...
  • Page 2 I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power- on for devices having reset function. SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and WINDOWS are trademarks of Microsoft Corporation.
  • Page 3 The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance.
  • Page 4 INTRODUCTION Targeted Reader This manual is intended for the user engineers who understand functions of the µ PD17120 subseries and design their application systems using the µ PD17120 sub- series Purpose The purpose of this manual is for the user to understand the hardware functions of the µ...
  • Page 5 Relevant Documents The following documents are provided for the µ PD17120 subseries. The numbers listed in the table are the document numbers. Some related documents are preliminary versions. This document, however, is not indicated as "Preliminary". Part Number µ PD17120 µ...

  • Page 6: Table Of Contents

    TABLE OF CONTENTS CHAPTER 1 GENERAL ........................FUNCTION LIST ........................ ORDERING INFORMATION ..................... BLOCK DIAGRAM ......................PIN CONFIGURATION (Top View) ................. CHAPTER 2 PIN FUNCTIONS ......................PIN FUNCTIONS ....................... 2.1.1 Pins in Normal Operation Mode ..................Pins in Program Memory Write/Verify Mode ... µ PD17P132, 17P133 only ..... 2.1.2 PIN INPUT/OUTPUT CIRCUIT ..................
  • Page 7 5.1.5 General Data Memory ......................5.1.6 Uninstalled Data Memory ....................CHAPTER 6 STACK ........................STACK CONFIGURATION ....................FUNCTIONS OF THE STACK ................... ADDRESS STACK REGISTER ..................INTERRUPT STACK REGISTER ..................STACK POINTER (SP) AND INTERRUPT STACK REGISTER ........STACK OPERATION DURING SUBROUTINES, TABLE REFERENCES, AND INTERRUPTS ......................
  • Page 8 CHAPTER 8 GENERAL REGISTER (GR) ..................GENERAL REGISTER CONFIGURATION................ FUNCTIONS OF THE GENERAL REGISTER ..............CHAPTER 9 REGISTER FILE (RF) ....................REGISTER FILE CONFIGURATION ................. 9.1.1 Configuration of the Register File ..................9.1.2 Relationship between the Register File and Data Memory ..........FUNCTIONS OF THE REGISTER FILE ................
  • Page 9 11.6 COMPARISON JUDGEMENT ..................11.6.1 “Equal to” Judgement ......................11.6.2 “Not Equal to” Judgement ....................11.6.3 “Greater Than or Equal to” Judgement ................11.6.4 “Less Than” Judgement ..................... 11.7 ROTATIONS ........................11.7.1 Rotation to the Right ......................11.7.2 Rotation to the Left ......................CHAPTER 12 PORTS ........................
  • Page 10 CHAPTER 14 INTERRUPT FUNCTIONS ..................14.1 INTERRUPT SOURCES AND VECTOR ADDRESS............14.2 HARDWARE COMPONENTS OF THE INTERRUPT CONTROL CIRCUIT ....14.2.1 Interrupt Request Flag (IRQ×××) and the Interrupt Enable Flag (IP×××) ......14.2.2 EI/DI Instruction ........................14.3 INTERRUPT SEQUENCE ....................14.3.1 Acceptance of Interrupts ....................
  • Page 11 18.5 INSTRUCTIONS......................... 18.5.1 Addition Instructions ......................18.5.2 Subtraction Instructions ...................... 18.5.3 Logical Operation Instructions .................... 18.5.4 Judgment Instruction ......................18.5.5 Comparison Instructions ..................... 18.5.6 Rotation Instructions ......................18.5.7 Transfer Instructions ......................18.5.8 Branch Instructions ......................18.5.9 Subroutine Instructions ....................... 18.5.10 Interrupt Instructions ......................18.5.11 Other Instructions ........................
  • Page 12 LIST OF FIGURES (1/2) Figure No. Title Page Program Counter ........................Value of the Program Counter after an Instruction Is Executed ..........Value in the Program Counter after Reset ................Value in the Program Counter during Execution of a Direct Branch Instruction ....Value in the Program Counter during Execution of an Indirect Branch Instruction ....
  • Page 13 LIST OF FIGURES (2/2) Figure No. Title Page 13-1 Configuration of the 8-bit Timer Counter ................13-2 Timer Mode Register ......................13-3 Setting the Count Value in a Modulo Register ............... 13-4 Error in Zero-Clearing the Count Registe during Counting ............ 13-5 Error in Starting Counting from the Count Halt State ............
  • Page 14 LIST OF TABLES (1/1) Table No. Title Page Handling Unused Pins ......................Vector Address for the µ PD17120 Subseries ................ Operation of the Stack Pointer ....................Operation of the Stack Pointer during Execution ..............Stack Operation during Table Reference ................Stack Operation during Interrupt Receipt and Return ............
  • Page 15 [MEMO] – x –...

  • Page 16: Chapter 1 General

    CHAPTER 1 GENERAL The µ PD17120, 17121, 17132 and 17133 are 4-bit single-chip microcontrollers employing the 17K architecture and containing 8-bit timer (1 channel), 3-wire serial interface, and power-on/power-down reset circuit. The µ PD17P132 and 17P133 are the one-time PROM version of the µ PD17132 and 17133, respectively, and are suitable for program evaluation at system development and for small-scale production.

  • Page 17: Function List

    CHAPTER 1 GENERAL 1.1 FUNCTION LIST Item µ PD17120 µ PD17132 µ PD17P132 µ PD17121 µ PD17133 µ PD17P133 Product Name Masked ROM One-time PROM Masked ROM One-time PROM ROM Capacity 1.5K bytes 2K bytes 1.5K bytes 2K bytes (768 × 16 bits) (1024 ×...

  • Page 18: Ordering Information

    CHAPTER 1 GENERAL 1.2 ORDERING INFORMATION Part Number Package Internal ROM µ PD17120CS-××× 24-pin plastic shrink DIP (300 mil) Mask ROM µ PD17120GT-××× 24-pin plastic SOP (375 mil) Mask ROM µ PD17121CS-××× 24-pin plastic shrink DIP (300 mil) Mask ROM µ...

  • Page 19: Block Diagram

    CHAPTER 1 GENERAL 1.3 BLOCK DIAGRAM • Block diagram of the µ PD17120 and 17121 Power On/ Power-Down Clock System Clock Reset Divider Generator CPU CLK CLK STOP (CMOS) 64 × 4 bits Interrupt SYSTEM REG. IRQTM Controller IRQSIO (CMOS) IRQTM Timer (CMOS)
  • Page 20 CHAPTER 1 GENERAL • Block diagram of µ PD17132, 17133, 17P132, and 17P133 Power On/ Note (CLK) Power-Down Clock System Clock Reset Divider Generator CPU CLK CLK STOP (CMOS) 111 × 4 bits Note INT (V Interrupt SYSTEM REG. IRQTM Controller IRQSIO (CMOS)

  • Page 21: Pin Configuration (Top View)

    CHAPTER 1 GENERAL 1.4 PIN CONFIGURATION (Top View) (1) Normal operating mode 24-pin plastic shrink DIP 24-pin plastic SOP Note 1 RESET /TMOUT /SCK Note 2 Note 2 Note 2 Note 2 pin for the µ PD17120 and 17121. Notes 1.
  • Page 22 CHAPTER 1 GENERAL (2) Program memory write/verify mode    Open         Caution ( ) represents processing of the pins which are not used in program memory write/verify mode. : Connect to GND via pull-down resistor one by one. Open : This pin should not be connected.
  • Page 23 [MEMO]...

  • Page 24: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTIONS 2.1.1 Pins in Normal Operation Mode Output At Power- Pin No. Symbol Function Format on/Reset Grounded – – µ PD17121, 17133, 17P133 • X Pins for system clock resonator oscillation Connected to ceramic resonator –...
  • Page 25 CHAPTER 2 PIN FUNCTIONS Output At Power- Pin No. Symbol Function Format on/Reset /SCK Port 0D, output of timer, serial data input, serial data N-ch Input output, serial clock input/output Open drain (P0D) • P0D to P0D 4-bit I/O port Input/output can be set per bit Pull-up resistor can be incorporated by each bit by Note...

  • Page 26: Pins In Program Memory Write/Verify Mode

    CHAPTER 2 PIN FUNCTIONS 2.1.2 Pins in Program Memory Write/Verify Mode ... µ PD17P132, 17P133 only Pin No. Symbol Function Grounded – Clock input for address updating in program memory writing/verifying Input Input for selecting operation mode in program memory writing/verifying Input 8-bit data input/output in program memory writing/verifying Input/Output...

  • Page 27: Pin Input/Output Circuit

    CHAPTER 2 PIN FUNCTIONS 2.2 PIN INPUT/OUTPUT CIRCUIT Below are simplified diagrams of the input/output circuits for each pin of the µ PD17120 subseries. (1) P0A -P0A , P0B -P0B Output Data latch P-ch N-ch Output disable Selector Input buffer...
  • Page 28 CHAPTER 2 PIN FUNCTIONS Note (2) P0C /Cin -P0C /Cin Output Data latch P-ch N-ch Output disable Input disable Selector Input buffer Analog (comparator) input are not included in the µ PD17120 and 17121. Note Pins Cin to Cin...
  • Page 29 CHAPTER 2 PIN FUNCTIONS (3) P0D -P0D Output Data latch Note Mask option N-ch Output disable Selector Input buffer Note The µ PD17P132 and 17P133 have no pull-up resistor by mask option, and are always open. (4) P0E Output Data latch Note Mask option...
  • Page 30 CHAPTER 2 PIN FUNCTIONS Note1 (5) P0E Output Data latch Note 2 Mask option Output N-ch disable enable Selector Input buffer 1. The µ PD17120 and 17121 have no V Notes pin function. 2. The µ PD17P132 and 17P133 have no pull-up resistor by mask option, and are always open. (6) INT Input buffer...
  • Page 31 CHAPTER 2 PIN FUNCTIONS (7) RESET Note Mask option Input buffer Note The µ PD17P132 and 17P133 have no pull-up resistor by mask option, and are always open.

  • Page 32: Handling Unused Pins

    CHAPTER 2 PIN FUNCTIONS 2.3 HANDLING UNUSED PINS In normal operation mode, it is recommended to process the unused pins as follows: Table 2-1. Handling Unused Pins Recommended Measures Pin Name Inside Microcontroller Outside Microcontroller P0A, P0B, P0C – Each pin is connected to V Does not incorporate a pull-up Note1 GND through the resistor.

  • Page 33: Cautions On Use Of The Reset And Int Pins (In Normal Operation Mode Only)

    CHAPTER 2 PIN FUNCTIONS 2.4 CAUTIONS ON USE OF THE RESET AND INT PINS (in Normal Operation Mode only) In addition to the function described in 2.1 PIN FUNCTIONS, the RESET pin and the INT pin have the function (for IC testing only) of setting test mode for testing the internal operation of the µ PD17120 subseries. If a voltage exceeding the V is applied to either of these pins, test mode is set.

  • Page 34: Chapter 3 Program Counter (Pc)

    CHAPTER 3 PROGRAM COUNTER (PC) The program counter is used to specify an address in program memory. 3.1 PROGRAM COUNTER CONFIGURATION Figure 3-1 shows the configuration of the program counter. The program counters are 10-bit binary counters. This program counter is incremented whenever an instruction is executed. Figure 3-1.

  • Page 35: Program Counter At Reset

    CHAPTER 3 PROGRAM COUNTER (PC) Figure 3-2. Value of the Program Counter after an Instruction Is Executed Program Counter Bit Program Counter Value Instruction PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 During reset BR addr Value set by addr CALL addr BR @AR CALL @AR...

  • Page 36: Program Counter During Execution Of Subroutine Calls (Call)

    CHAPTER 3 PROGRAM COUNTER (PC) Figure 3-5. Value in the Program Counter during Execution of an Indirect Branch Instruction 3.2.3 Program Counter during Execution of Subroutine Calls (CALL) There are two ways to specify branching using subroutine calls. One is to specify the branch address in the operand using the direct subroutine call (CALL addr).

  • Page 37: Program Counter During Execution Of Return Instructions (Ret, Retsk, Reti)

    CHAPTER 3 PROGRAM COUNTER (PC) 3.2.4 Program Counter during Execution of Return Instructions (RET, RETSK, RETI) During execution of a return instruction (RET, RETSK, RETI), the program counter is restored to the value saved in the address stack register. Figure 3-8. Value in the Program Counter during Execution of a Return Instruction Address stack register n (n = 0 to 4) 3.2.5 Program Counter during Table Reference (MOVT)

  • Page 38: Chapter 4 Program Memory (Rom)

    CHAPTER 4 PROGRAM MEMORY (ROM) The program configuration of the µ PD17120 subseries is as follows. Product Name Program Memory Capacity Program Memory Address µ PD17120 1.5K bytes (768 × 16 bits) 0000H-02FFH µ PD17121 µ PD17132 µ PD17133 2K bytes (1024 × 16 bits) 0000H-03FFH µ...

  • Page 39: Program Memory Usage

    CHAPTER 4 PROGRAM MEMORY (ROM) 4.2 PROGRAM MEMORY USAGE Program memory has the following two main functions: (1) Storage of the program (2) Storage of constant data The program is made up of the instructions which operate the CPU (Central Processing Unit). The CPU executes sequential processing according to the instructions stored in the program.
  • Page 40 CHAPTER 4 PROGRAM MEMORY (ROM) Table 4-1. Vector Address for the µ PD17120 Subseries Vector Address Interrupt Sources 0000H Reset 0001H Serial interface interrupt 0002H Timer interrupt 0003H External interrupt (INT pin) (2) Direct branch When executing a direct branch (BR addr), the 11-bit instruction operand is used to specify an address in program memory.
  • Page 41 CHAPTER 4 PROGRAM MEMORY (ROM) Example Figure 4-2. Direct Subroutine Call (CALL addr) Program memory Adddress 0000H CALL SUB1 SUB1: Note 03FFH Note The last address of the program memory of the µ PD17120 and µ PD17121 is 02FFH. (5) Indirect subroutine call When using an indirect subroutine call (CALL @AR), the value in the address register (AR) should be an address of the called subroutine.
  • Page 42 CHAPTER 4 PROGRAM MEMORY (ROM) 4.2.2 Table Reference Table reference is used to reference constant data in program memory. The table reference instruction (MOVT DBF, @AF) is used to store the contents of the program memory address specified by the address register in the data buffer. Since each location in program memory contains 16 bits of information, the MOVT instruction causes 16 bits of data to be stored in the data buffer.
  • Page 43 CHAPTER 4 PROGRAM MEMORY (ROM) (1) Constant data table Example 1 shows an example of code used to reference a constant data table. Example 1. Code used for reading the values recorded in a constant data table. The value specified by an OFFSET value is read.
  • Page 44 CHAPTER 4 PROGRAM MEMORY (ROM) (2) Branch table Example 2 shows an example of code used to reference a branch table. Example 2. Code used for reading the values recorded in a branch table. The value specified by an OFFSET value is read. OFFSET 0.00H ;...
  • Page 45 [MEMO]...

  • Page 46: Chapter 5 Data Memory (Ram)

    CHAPTER 5 DATA MEMORY (RAM) Data memory stores data such as operation and control data. Data can be read from or written to data memory with an instruction during normal operation. 5.1 DATA MEMORY CONFIGURATION Figure 5-1 shows the configuration of data memory. Data memory is controlled by the concept called banks.

  • Page 47: System Register (Sysreg)

    CHAPTER 5 DATA MEMORY (RAM) 5.1.1 System Register (SYSREG) The system register (SYSREG) consists of the 12 nibbles allocated at addresses 74H to 7FH in data memory. The system register (SYSREG) is allocated independently of the banks. This means that each bank has the same system register at addresses 74H to 7FH.

  • Page 48: Port Registers

    CHAPTER 5 DATA MEMORY (RAM) Figure 5-4. General Register (GR) Configuration BANK0 Column address General register Area specifiable as general register Pointed to by general register pointer (RP) in system register. Note that row addresses 4 to 6 µ in the case of the PD17120 and 17121 are uninstalled mem- ory locations.
  • Page 49 [MEMO]...

  • Page 50: Chapter 6 Stack

    CHAPTER 6 STACK The stack is a register used to save information such as the program return address and the contents of the system register during execution of subroutine calls, interrupts and similar operations. 6.1 STACK CONFIGURATION Figure 6-1 shows the stack configuration. The stack consists of the following parts: one 3-bit binary counter stack pointer, five 10-bit address stack registers, and one 5-bit interrupt stack registers.

  • Page 51: Address Stack Register

    CHAPTER 6 STACK 6.3 ADDRESS STACK REGISTER As shown in Figure 6-1, the address stack register consists of five consecutive 10-bit registers. A value equal to the program counter (PC)+1 (return address) is stored during execution of subroutine calls (CALL addr, CALL @AR), the first cycle of a table reference (MOVT DBF, @AR), and upon receipt of an interrupt in the address stack register.

  • Page 52: Stack Operation During Subroutines, Table References, And Interrupts

    CHAPTER 6 STACK Table 6-1. Operation of the Stack Pointer Instruction Stack Pointer Value Counter of Interrupt Stack Register CALL addr CALL @AR MOVT DBF, @AR –1 Not changed (1st instruction cycle) PUSH AR Interrupt receipt –1 –1 RETSK MOVT DBF, @AR Not changed (2nd instruction cycle) POP AR...

  • Page 53: Stack Operation During Table Reference (Movt Dbf, @Ar)

    CHAPTER 6 STACK Table 6-2. Operation of the Stack Pointer during Execution Instruction Operation CALL addr <1> Stack pointer (SP) is decremented. <2> Program counter (PC) is saved in the address stack register pointed to by the stack pointer (SP). <3>...

  • Page 54: Executing Reti Instruction

    CHAPTER 6 STACK 6.6.3 Executing RETI Instruction Table 6-4 shows stack operation during interrupt receipt and RETI instruction execution. Table 6-4. Stack Operation during Interrupt Receipt and Return Instruction Operation Receipt of interrupt <1> Stack pointer (SP) is decremented. <2> Value in the program counter (PC) is saved in the address stack register pointed to by the stack pointer (SP).
  • Page 55 [MEMO]...

  • Page 56: Chapter 7 System Register (Sysreg)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) The system register (SYSREG), located in data memory, is used for direct control of the CPU. 7.1 SYSTEM REGISTER CONFIGURATION Figure 7-1 shows the allocation address of the system register in data memory. As shown in Figure 7-1, the system register is allocated in addresses 74H to 7FH of data memory.
  • Page 57 CHAPTER 7 SYSTEM REGISTER (SYSREG) Figure 7-2 shows the configuration of the system register. As shown in Figure 7-2, the system register consists of the following seven registers. • Address register (AR) • Window register (WR) • Bank register (BANK) •...

  • Page 58: Address Register (Ar)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.2 ADDRESS REGISTER (AR) 7.2.1 Address Register Configuration Figure 7-3 shows the configuration of the address register. As shown in Figure 7-3, the address register consists of the sixteen bits in address 74H to 77H (AR3 to AR0) of the system register.

  • Page 59: Address Register Used As A Peripheral Register

    CHAPTER 7 SYSTEM REGISTER (SYSREG) (2) Stack manipulation instructions (PUSH AR, POP AR) When the PUSH AR instruction is executed, the stack pointer (SP) is first decremented and then the address register is stored in the address stack pointed to by the stack pointer. When the POP AR instruction is executed, the contents of the address stack pointed to by the stack pointer is transferred to the address register and then the stack pointer is incremented.

  • Page 60: Window Register (Wr)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.3 WINDOW REGISTER (WR) 7.3.1 Window Register Configuration Figure 7-5 shows the configuration of the window register. As shown in Figure 7-5, the window register (WR) consists of four bits allocated at address 78H of the system register.

  • Page 61: Bank Register (Bank)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.4 BANK REGISTER (BANK) Figure 7-6 shows the configuration of the bank register. The bank register consists of four bits at address 79H (BANK) of the system register. Bank register is a register for switching the banks of RAM. However, since the µ PD17120 subseries has only one bank, every bank register bit is fixed to 0.

  • Page 62: Index Register (Ix) And Data Memory Row Address Pointer (Memory Pointer: Mp)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (Memory Pointer: MP) 7.5.1 Index Register (IX) IX is used for address modification to data memory. It differs from MP in that its modification object is an address that is specified as the bank or operand m.
  • Page 63 CHAPTER 7 SYSTEM REGISTER (SYSREG) Figure 7-7. Index Register and Memory Pointer Configuration Address Program status Index register (IX) word Name (PSWORD)'S Memory pointer (MP) lower 4 bits Symbol name Flag name (IX) (MP) Data Reset-time value Figure 7-8. Data Memory Address Modification by Index Register and Memory Pointer Data Memory Address Specified with m Indirect Transfer Address Specified with @m Bank...
  • Page 64 CHAPTER 7 SYSTEM REGISTER (SYSREG) Table 7-1. Address-modified Instruction Statements r, m ADDC ------------------------------------------------------------ m, #n4 SUBC r, m ------------------------------------------------------------ m, #n4 m, #n SKGE m, #n4 SKLT SKNE r, m m, r m, #n4 ------------------------------------------------------------ @r, m m, @r...

  • Page 65: Mpe=0 And Ixe=0 (No Data Memory Modification)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.5.3 MPE=0 and IXE=0 (No Data Memory Modification) As shown in Figure 7-8, data memory addresses are not affected by the index register and the data memory row address pointer. (1) Data memory manipulation instructions Example 1.
  • Page 66 CHAPTER 7 SYSTEM REGISTER (SYSREG) Example 3. General register is in row address 0 R00B 0.0BH M034 0.34H ; R00B ← 0EH R00B, #0EH M034, @R00B ; Indirect transfer of data in the register As shown in Figure 7-9, when the above instructions are executed, the contents of data memory stored at address 3EH is transferred to data memory location M034.

  • Page 67: Mpe=1 And Ixe=0 (Diagonal Indirect Data Transfer)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.5.4 MPE=1 and IXE=0 (Diagonal Indirect Data Transfer) As shown in Figure 7-8, the indirect data transfer bank and row address specified by @r become the data memory row address pointer value only when general register indirect data transfer instructions (MOV @r, m and MOV m, @r) are used.
  • Page 68 CHAPTER 7 SYSTEM REGISTER (SYSREG) Example 2. General register is in row address 0 R00B 0.0BH M034 0.34H ; MP ← 6 MPL, #0110B ; MPE ← 1 MPH, #1000B ; R00B ← 0EH R00B, #0EH M034, @R00B ; Indirect transfer of data in the register As shown in Figure 7-10, when the above instructions are executed, the data stored in address 6EH is transferred to data memory location M034.

  • Page 69: Mpe=0 And Ixe=1 (Index Modification)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.5.5 MPE=0 and IXE=1 (Index Modification) As shown in Figure 7-8, when a data memory manipulation instruction is executed, any bank or address in data memory specified by m can be modified using the index register. When indirect data transfer using the general register (MOV @r, m or MOV m, @r) is executed, the indirect transfer bank and address specified by @r can be modified using the index register.
  • Page 70 CHAPTER 7 SYSTEM REGISTER (SYSREG) Figure 7-11. Example of Operation When MPE=0 and IXE=1 Column address General R003 register Example 1. ADD @R003, M061 Index modification M061 : 00001100001B : 00000010010B Real address 00001110011B M061 System register Addresses in Example 1 ADD R003, M061 Column Bank...
  • Page 71 CHAPTER 7 SYSTEM REGISTER (SYSREG) Example 2. Indirect data transfer using the general register Assume that the general register is row address 0. R005 0.05H M034 0.34H IX ← 00000000001B IXL, #0001B IXM, #0000B MPE ← 0 IXH, #0000B IXE ← 1 PSW, #.DF.IXE AND 0FH ;...

  • Page 72: Example Of Operation When Mpe=0 And Ixe=0

    CHAPTER 7 SYSTEM REGISTER (SYSREG) Figure 7-12. Example of Operation When MPE=0 and IXE=1 Column address General R005 register Column address specified as transfer destination M034 Example 2. MOV @R005, M034 Direct Indirect address Index modification address M034 : 00000110100B : 00000000001B Real address 00000110101B System register...
  • Page 73 CHAPTER 7 SYSTEM REGISTER (SYSREG) Example 4. Processing an array As shown in Figure 7-13, to perform the operation: A(N) = A(N) + 4 (0 ≤ N ≤ 15) on the element A(N) of a one-dimensional array in which an element is 8 bits, the following instructions are executed: M000 MEM 0.00H...

  • Page 74: General Register Pointer (Rp)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.6 GENERAL REGISTER POINTER (RP) 7.6.1 General Register Pointer Configuration Figure 7-14 shows the configuration of the general register pointer. Figure 7-14. General Register Pointer Configuration Address General register Name pointer (RP) Symbol Flag Data (RP) Initial value when reset As shows in Figure 7-14, the general register pointer consists of seven bits;...

  • Page 75: Functions Of The General Register Pointer

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.6.2 Functions of the General Register Pointer The general register pointer is used to specify the location of the general register in data memory. For a more detailed explanation, refer to CHAPTER 8 GENERAL REGISTER (GR). The general register consists of sixteen nibbles in any single row of data memory.

  • Page 76: Program Status Word (Psword)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.7 PROGRAM STATUS WORD (PSWORD) 7.7.1 Program Status Word Configuration Figure 7-16 shows the configuration of the program status word. Figure 7-16. Program Status Word Configuration Address Program status Name word (PSWORD) (RP) Symbol Data Initial value when reset As shown in Figure 7-16, the program status word consists of five bits;...

  • Page 77: Functions Of The Program Status Word

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.7.2 Functions of the Program Status Word The flags of the program status word are used for setting conditions for arithmetic/logical operations and data transfer instructions and for reflecting the status of operation results. Figure 7-17 shows an outline of the functions of the program status word.

  • Page 78: Index Enable Flag (Ixe)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.7.3 Index Enable Flag (IXE) The IXE flag is used to enable to modify index of the data memory address, whether index modification is to be performed on the data memory address used. For a more detailed explanation, refer to 7.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MEMORY POINTER: MP).

  • Page 79: Carry Flag (Cy)

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.7.5 Carry Flag (CY) The CY flag shows whether there is a carry in the result of an addition operation or a borrow in the result of a subtraction operation. The CY flag is set (CY=1) when there is a carry or borrow in the result and reset (CY=0) when there is no carry or borrow in the result.

  • Page 80: Cautions On Use Of The System Register

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.8 CAUTIONS ON USE OF THE SYSTEM REGISTER 7.8.1 Reserved Words for Use with the System Register Because the system register is allocated in data memory, it can be used in any of the data memory manipulation instructions.
  • Page 81 CHAPTER 7 SYSTEM REGISTER (SYSREG) By using these macro instructions, data memory can be handled as flags as shown below in Example 3. The functions of the program status word and the memory pointer enable flag are defined in bit units (flag units) and each bit has a reserved word MPE, BCD, CMP, CY, Z and IXE defined for it.

  • Page 82: Handling Of System Register Addresses Fixed At

    CHAPTER 7 SYSTEM REGISTER (SYSREG) 7.8.2 Handling of System Register Addresses Fixed at 0 In dealing with system register addresses fixed at 0 (refer to Figure 7-2), there are a few points for which caution should be taken with regard to device, emulator and assembler operation. Items (1), (2) and (3) explain these points.
  • Page 83 CHAPTER 7 SYSTEM REGISTER (SYSREG) (3) When using a 17K series assembler (AS17K) No error is output when an attempt is made to write the value 1 to a bit fixed at 0. The instruction shown in Example 1 MOV BANK, #0100B will not cause an assembler error.

  • Page 84: Chapter 8 General Register (Gr)

    CHAPTER 8 GENERAL REGISTER (GR) The general register (GR) is allocated in data memory. It can therefore be used directly in performing arithmetic/ logical operations with and in transferring data to and from general data memory. 8.1 GENERAL REGISTER CONFIGURATION Figure 8-1 shows the configuration of the general register.
  • Page 85 CHAPTER 8 GENERAL REGISTER (GR) Figure 8-1. General Register Configuration BANK0 Column address General General register (16 nibbles) register The general register when pointer (RP) can be used RPH=0000B to specify any row RPL=010×B address in address locations 0H to 7H System register Address General register pointer...

  • Page 86: Chapter 9 Register File (Rf)

    CHAPTER 9 REGISTER FILE (RF) The register file is a register used mainly for specifying conditions for peripheral hardware. 9.1 REGISTER FILE CONFIGURATION 9.1.1 Configuration of the Register File Figure 9-1 shows the configuration of the register file. As shown in Figure 9-1, the register file is a register consisting of 128 nibbles (128 words × 4 bits). In the same way as with data memory, the register file is divided into address in units of four bits.

  • Page 87: Functions Of The Register File

    CHAPTER 9 REGISTER FILE (RF) Figure 9-2. Relationship Between the Register File and Data Memory Column address 1 2 3 4 5 6 7 8 9 A B C D E F Data memory BANK0 Port register System register Control register Register file 9.2 FUNCTIONS OF THE REGISTER FILE 9.2.1 Functions of the Register File...

  • Page 88: Register File Manipulation Instructions

    CHAPTER 9 REGISTER FILE (RF) 9.2.3 Register File Manipulation Instructions Reading and writing data to and from the register file is done using the window register (WR: address 78H) located in the system register. Reading and writing of data is performed using the following dedicated instructions: PEEK WR, rf: Read the data in the address specified by rf and put it into WR.
  • Page 89 CHAPTER 9 REGISTER FILE (RF) Figure 9-3 shows an example of register file operation. As shown in Figure 9-3, reading and writing of data to and from the control register (address locations 00H to 3FH) is performed using the "PEEK WR, rf" and "POKE rf, WR" instructions. Data within the control register specified using rf can be read from and written to the control register, only by using these instructions with the window register.

  • Page 90: Control Register

    CHAPTER 9 REGISTER FILE (RF) 9.3 CONTROL REGISTER The control register consists of 64 nibbles (64 × 4 bits) allocated in register file address locations 00H to 3FH. Of these nibbles, only 17 nibbles are actually used in the µ PD17120 and 17121, and 20 nibbles are used in the µ...

  • Page 91: Register File Symbol Definitions And Reserved Words

    CHAPTER 9 REGISTER FILE (RF) (3) During use of the in-circuit emulator (IE-17K or IE-17K-ET) (operation during patch processing and similar operations) Attempting to write to a read-only register has no effect and no error is generated. Attempting to read data from an address in the unused data area will yield an unpredictable value. Attempting to write to an address in the unused data area has no effect and no error is generated.
  • Page 92 CHAPTER 9 REGISTER FILE (RF) The assembler (AS17K) has the below flag symbol handling instructions defined internally as macros. SETn: Set a flag to 1 CLRn: Reset a flag to 0 SKTn: Skip when all flags are 1 SKFn: Skip when all flags are 0 NOTn: Invert a flag INITFLG: Initialize a flag (data setting per 4 bits)
  • Page 93 [MEMO]...

  • Page 94: Chapter 10 Data Buffer (Dbf)

    CHAPTER 10 DATA BUFFER (DBF) The data buffer consists of four nibbles allocated in addresses 0CH to 0FH in BANK0. The data buffer is used as a data storage area when data is transferred to/from the CPU peripheral circuit (address register, serial interface, and timer) by the GET and PUT instructions.

  • Page 95: Functions Of The Data Buffer

    CHAPTER 10 DATA BUFFER (DBF) Figure 10-2. Data Buffer Configuration Address Data memory BANK0 Symbol DBF3 DBF2 DBF1 DBF0 Data buffer Data Data Because the data buffer is allocated in data memory, it can be used in any of the data memory manipulation instructions.

  • Page 96: Data Buffer And Peripheral Hardware

    CHAPTER 10 DATA BUFFER (DBF) 10.2.1 Data Buffer and Peripheral Hardware Table 10-1 shows data transfer with peripheral hardware using the data buffer. Each unit of peripheral hardware has an individual address (called its peripheral address). By using this peripheral address and the dedicated instructions GET and PUT, data can be transferred between each unit of peripheral hardware and the data buffer.

  • Page 97: Data Transfer With Peripheral Hardware

    CHAPTER 10 DATA BUFFER (DBF) 10.2.2 Data Transfer with Peripheral Hardware Data can be transferred between the data buffer and peripheral hardware in 8- or 16-bit units. Instruction cycle for a single PUT or GET instruction is the same regardless of whether eight or sixteen bits are being transferred. Example 1.
  • Page 98 CHAPTER 10 DATA BUFFER (DBF) 10.2.3 Table Reference By using the MOVT instruction, constant data in program memory (ROM) can be read into the data buffer. The MOVT instruction is explained below. MOVT DBF, @AR: The contents of the program memory being pointed to by the address register (AR) is read into the data buffer (DBF).
  • Page 99 [MEMO]...

  • Page 100: Chapter 11 Arithmetic And Logic Unit

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT The ALU is used for performing arithmetic operations, logical operations, bit evaluations, comparison evaluations, and rotations on 4-bit data. 11.1 ALU BLOCK CONFIGURATION Figure 11-1 shows the configuration of the ALU block. As shown in Figure 11-1, the ALU block consists of the main 4-bit data processor, temporary registers A and B, the status flip-flop for controlling the status of the ALU, and the decimal conversion circuit for use during arithmetic operations in BCD.
  • Page 101 CHAPTER 11 ARITHMETIC AND LOGIC UNIT Figure 11-1. Configuration of the ALU Data bus Temporary Temporary Status register A register B flip-flop • Arithmetic operations • Logical operations • Bit evaluations •Comparison evaluations •Rotations Decimal con- version circuit Address Program status word Name (PSWORD) Flag...
  • Page 102 CHAPTER 11 ARITHMETIC AND LOGIC UNIT [MEMO]...
  • Page 103 CHAPTER 11 ARITHMETIC AND LOGIC UNIT Table 11-1. List of ALU Instructions (1/2) ALU Functions Instruction Operation Explanation (r) ← (r) + (m) Arith- Addi- ADD r, m Adds contents of general register and data memory. metic tion Result is stored in general register. opera- (m) ←...
  • Page 104 CHAPTER 11 ARITHMETIC AND LOGIC UNIT Table 11-1. List of ALU Instructions (2/2) ALU Function Operational Variance Depending on Program Status Word (PSWORD) Arithmetic Modifica- Operation BCD flag's CMP flag's Operating CY flag Z flag tion by value value action IXE=1 The binary Set if a...

  • Page 105: Functions Of Temporary Registers A And B

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.2.2 Functions of Temporary Registers A and B Temporary registers A and B are needed for processing of 4-bit data. These registers are used for temporary storage of the first and second data operands of an instruction. 11.2.3 Functions of the Status Flip-flop The status flip-flop is used for controlling operation of the ALU and for storing data which has been processed.

  • Page 106: Performing Operations In 4-Bit Binary

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT (3) CMP flag When the CMP flag is set (1), the result of an arithmetic operation is not stored in either the general register or data memory. When the bit evaluation instruction is performed, the CMP flag is reset (0). The CMP flag does not affect comparison evaluations, logical operations, or rotations.
  • Page 107 CHAPTER 11 ARITHMETIC AND LOGIC UNIT Table 11-2. Results of Arithmetic Operations Performed in 4-Bit Binary and BCD Addition in Addition in Subtraction in Subtraction in 4-bit Binary 4-bit Binary Operation Operation Operation Operation Result Result Operation Operation Result Result Result Result 0000...

  • Page 108: Performing Operations In The Alu Block

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.2.6 Performing Operations in the ALU Block When arithmetic operations, logical operations, bit evaluations, comparison evaluations or rotations in a program are executed, the first data operand is stored in temporary register A and the second data operand is stored in temporary register B.

  • Page 109: Arithmetic Operations (Addition And Subtraction In 4-Bit Binary And Bcd)

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT Caution should be taken with regard to the following points: (1) Arithmetic operations are affected by the CMP and BCD flags in the program status word. (2) Logical operations are not affected by the CMP or BCD flag in the program status word. Logical operations do not affect the Z or CY flags.

  • Page 110: Addition And Subtraction When Cmp=0 And Bcd=0

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.3.1 Addition and Subtraction When CMP=0 and BCD=0 Addition and subtraction are performed in 4-bit binary and the result is stored in the general register or data memory. When the result of the operation is greater than 1111B (carry generated) or less than 0000B (borrow generated), the CY flag is set (1);...

  • Page 111: Addition And Subtraction When Cmp=1 And Bcd=1

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.3.4 Addition and Subtraction When CMP=1 and BCD=1 BCD operations are performed. The result is not stored in either the general register or data memory. In other words, the operations specified by CMP=1 and BCD=1 are both performed at the same time. Example RPL, #0001B ;...

  • Page 112: Bit Judgement

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT Table 11-4. Logical Operations Logical Logical OR General register and data memory OR r, m operation Data memory and immediate data OR m, #n4 Logical AND General register and data memory AND r, m Data memory and immediate data AND m, #n4 Logical XOR General register and data memory XOR r, m...

  • Page 113: True (1) Bit Judgement

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.5.1 TRUE (1) Bit Judgement The TRUE (1) bit judgement instruction (SKT m, #n) is used to determine whether or not the bits specified by n in the four bits of data memory m are TRUE (1). When all bits specified by n are TRUE (1), this instruction causes the next instruction to be skipped.

  • Page 114: Comparison Judgement

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.6 COMPARISON JUDGEMENT As shown in Table 11-7, there are comparison judgement instructions for determining if one value is "equal to", "not equal to", "greater than or equal to", or "less than" another. The SKE instruction is used to determine if two values are equal. The SKNE instruction is used to determine two values are not equal.

  • Page 115: Equal To" Judgement

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.6.1 "Equal to" Judgement The "equal to" judgement instruction (SKE m, #n4) is used to determine if immediate data and the contents of a location in data memory are equal. This instruction causes the next instruction to be skipped when the immediate data and the contents of data memory are equal.

  • Page 116: Greater Than Or Equal To" Judgement

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.6.3 "Greater Than or Equal to" Judgement The "greater than or equal to" judgement instruction (SKGE m, #n4) is used to determine if the contents of a location in data memory is a value greater than or equal to the value of the immediate data operand. If the value in data memory is greater than or equal to that of the immediate data, this instruction causes the next instruction to be skipped.

  • Page 117: Rotations

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.7 ROTATIONS There are rotation instructions for rotation to the right and for rotation to the left. The RORC instruction is used for rotation to the right. The RORC instruction can only be used with the general register. Rotation using the RORC instruction is not affected by the BCD or CMP flags in the program status word (PSWORD) and does not affect the Z flag in the program status word (PSWORD).

  • Page 118: Rotation To The Left

    CHAPTER 11 ARITHMETIC AND LOGIC UNIT 11.7.2 Rotation to the Left Rotation to the left is performed by using the addition instruction, "ADDC r, m". Example #0000B ; Resets CY flag to 0. #1000B #0100B #0010B ADDC R3, R3 ADDC R2, R2 ADDC R1, R1...
  • Page 119 [MEMO]...

  • Page 120: Chapter 12 Ports

    CHAPTER 12 PORTS 12.1 PORT 0A (P0A , P0A , P0A , P0A Port 0A is a 4-bit input/output port with an output latch. It is mapped into address 70H of BANK0 in data memory. The output format is CMOS push-pull output. Input or output can be specified in each bit.

  • Page 121: Port 0B (P0B , P0B 1 , P0B 2 , P0B 3 )

    CHAPTER 12 PORTS 12.2 PORT 0B (P0B , P0B , P0B , P0B Port 0B is a 4-bit input/output port with an output latch. It is mapped into address 71H of BANK0 in data memory. The output format is CMOS push-pull output. Input or output can be specified in 4-bit units.

  • Page 122: Port 0C (P0C , P0C , P0C , P0C )

    CHAPTER 12 PORTS ) ... in the case of the µ PD17120 and 17121 12.3 PORT 0C (P0C , P0C , P0C , P0C Port 0C is a 4-bit input/output port with an output latch. It is mapped into address 72H of BANK0 in data memory. The output format is CMOS push-pull output.

  • Page 123: Port 0C

    CHAPTER 12 PORTS 12.4 PORT 0C (P0C /Cin , P0C /Cin , P0C /Cin , P0C /Cin ... in the case of the µ PD17132, 17133, 17P132, and 17P133 Port 0C is a 4-bit input/output port with an output latch. It is mapped into address 72H of BANK0 in data memory. The output format is CMOS push-pull output.

  • Page 124: Port P0D (Pp0D /Sck, Pp0D /So, Pp0D /Si, Pp0D /Tmout)

    CHAPTER 12 PORTS 12.5 PORT 0D (P0D /SCK, P0D /SO, P0D /SI, P0D /TMOUT) Port 0D is a 4-bit input/output port with an output latch. It is mapped into address 73H of BANK0 in data memory. The output format is N-ch open-drain output. The mask option can be used to specify that a pin contain a pull-up Note resistor bit-by-bit Input or output can be specified bit-by bit.
  • Page 125 CHAPTER 12 PORTS Table 12-5. Register File Contents and Pin Functions (n=0 to 3) Register File Value Pin Function TMOSEL SIOEN P0DBIOn RF: 12H RF: 0AH RF: 33H /SCK /TMOUT Bit 0 Bit 0 Bit n Input port Output port Input port Output port Input port...

  • Page 126: Port 0E (P0E0, P0E1/V ) ... V , Μ Pd17132, 17133, 17P132, And 17P133 Only

    CHAPTER 12 PORTS ; µ PD17132, 17133, 17P132, and 17P133 only 12.6 PORT 0E (P0E , P0E ) ... V Port 0E is a 2-bit input/output port with an output latch. It is mapped into bits 0 and 1 of address 6FH in data memory.

  • Page 127: Cautions When Operating Port Registers

    CHAPTER 12 PORTS 12.6.1 Cautions when Operating Port Registers Among the input/output ports in the µ PD17120 series, only port 0E is such that, even when in output mode, doing a read causes the status of the pins to be read. Consequently, when executing port register read macro instructions (SETn/CLRn, etc.) or bit manipulation instructions such as AND/OR/XOR, etc., you may inadvertently change the status of the pins.

  • Page 128: Port Control Register

    CHAPTER 12 PORTS 12.7 PORT CONTROL REGISTER 12.7.1 Input/Output Switching by Group I/O Ports which switch input/output in units of four bits are called group I/O. Port 0B is used as group I/O. The register shown in the figure below is used for input/output switching. Figure 12-2.

  • Page 129: Input/Output Switching By Bit I/O

    CHAPTER 12 PORTS 12.7.2 Input/Output Switching by Bit I/O Ports which switch input/output bit-by-bit are called bit I/O. Port 0A, port 0C, port 0D, and port 0E are used as bit I/O. The register shown in the figure below is used for input/output switching. Figure 12-3.
  • Page 130 CHAPTER 12 PORTS Figure 12-3. Bit I/O Port Control Register (2/4) RF: 34H Bit 3 Bit 2 Bit 1 Bit 0 P0CBIO3 P0CBIO2 P0CBIO1 P0CBIO0 Read/write Read=R, write=W Initial value when reset P0CBIO0 Function Sets P0C to input mode. Sets P0C to output mode.
  • Page 131 CHAPTER 12 PORTS Figure 12-3. Bit I/O Port Control Register (3/4) RF: 33H Bit 3 Bit 2 Bit 1 Bit 0 P0DBIO3 P0DBIO2 P0DBIO1 P0DBIO0 Read/write Read=R, write=W Initial value when reset P0DBIO0 Function Sets P0D to input mode. Sets P0D to output mode.

  • Page 132: Chapter 13 Peripheral Hardware

    CHAPTER 13 PERIPHERAL HARDWARE 13.1 8-BIT TIMER COUNTER (TM) The µ PD17120 subseries contains an 8-bit timer counter system. Control of the 8-bit timer counter is performed through hardware manipulation using the PUT/GET instruction or through register manipulation on the register file using the PEEK/POKE instruction.
  • Page 133 Figure 13-1. Configuration of the 8-bit Timer Counter Data buffer (DBF) Internal bus Timer carry Bit I/O port Timer mode register Interrupt control output control control register (RF : 11H) register (RF : 0FH) mode register (RF : 33H) (RF : 12H) TMEN TMRES TMCK1...

  • Page 134: 8-Bit Timer Counter Control Register

    CHAPTER 13 PERIPHERAL HARDWARE 13.1.2 8-bit Timer Counter Control Register There are two types of 8-bit timer counter control registers; timer mode register and timer carry output control mode register. Figures 13-2 and 13-3 show the configuration of 8-bit timer counter control registers. Figure 13-2.

  • Page 135: Operation Of 8-Bit Timer Counters

    CHAPTER 13 PERIPHERAL HARDWARE 13.1.3 Operation of 8-bit Timer Counters (1) Count Register Count register are 8-bit up counters whose initial values are 00H. They are incremented each time a count pulse is entered. The counter register is initialized in the following situations: •...

  • Page 136: Setting A Count Value In Modulo Register And Calculation Method

    CHAPTER 13 PERIPHERAL HARDWARE 13.1.5 Setting a Count Value in Modulo Register and Calculation Method Count value is set in the module register via the data buffer (DBF). (1) Setting the count value in modulo register A count value is set in the modulo register via the data buffer using the PUT instruction. The peripheral address of the modulo register is 03H.
  • Page 137 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-3. Setting the Count Value in a Modulo Register Example of setting count value 64H in timer modulo register CONTDATL ; CONTDATL is assigned to 4H using the symbol definition instruction. CONTDATH ; CONTDATH is assigned to 6H using the symbol definition instruction. MOV DBF0, #CONTDATL;...
  • Page 138 CHAPTER 13 PERIPHERAL HARDWARE (2) Calculation method of count value The time interval of the identity signal being emitted from the comparator is determined by the value that is set in the modulo register. The formula for finding the value N of the modulo register from the time interval T [sec] is shown below: = (N+1) ×...

  • Page 139: Margin Of Error Of Interval Time

    CHAPTER 13 PERIPHERAL HARDWARE (Program example) DBF0, #0AH ; Stores DAH to DBF by using DBF1, #0DH ; reserved words "DBF0" and "DBF1" TMM, ; Transfers the contents of DBF by using reserved word "TMM" INITFLG TMEN, TMRES, NOT TMCK1, NOT TMCK0 ;...
  • Page 140 CHAPTER 13 PERIPHERAL HARDWARE (2) Error in Starting Counting from the Count Halt State The count register of the 8-bit timer counter is cleared to zero by setting (to 1) the TMRES flag; however, the scaler for generating the count pulse from the system clock is not reset. When the TMEN flag is set (to 1) to start the counting from the count halt status, the timing of the first count varies as follows depending on whether the count pulse is started from the low level or from the high level.

  • Page 141: Reading Count Register Values

    CHAPTER 13 PERIPHERAL HARDWARE (b) When the count pulse is started from the low level (error: –1 to –1.5 counts) Counting start (TMEN = 1←0) 0.5 to 1count 2 counts Count pulse Count register Match signal output Match signal output In the example above, the identity signal is generated every 2 counts;...
  • Page 142 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-6. Reading 8-Bit Counter Count Values The timer counter value is F0H. GET DBF, TMC; Example of using reserved words DBF and TMC Data Buffer DBF3 DBF2 DBF1 DBF0 Retained Retained GET DBF, TMC 8-bit data TMC (Peripheral Address 02H) Count value (2) Program example...
  • Page 143 CHAPTER 13 PERIPHERAL HARDWARE INITFLG NOT IEGMD1, IEGMD0 ; Sets input from INT pin to falling edge CLR1 ; Clears interrupt request signal from INT pin INITFLG TMEM, TMRES, NOT TMCK1, TMCK0 ; Sets source clock of timer to "f /32"...

  • Page 144: Timer Output

    CHAPTER 13 PERIPHERAL HARDWARE 13.1.8 Timer Output The P0D /TMOUT pin functions as a timer match signal output pin when the TMOSEL flag is set to 1. The P0DBIO3 value has nothing to do with this setting. Timer contains a match signal output flip-flop. It reverses the output each time the comparator outputs a match signal.

  • Page 145: Timer Resolution And Maximum Setting Time

    CHAPTER 13 PERIPHERAL HARDWARE 13.1.9 Timer Resolution and Maximum Setting Time Table 13-1 shows the timer resolution in each source clock and maximum setting time. Table 13-1. Timer Resolution and Maximum Setting Time Mode Register Timer System Clock TMCK1 TMCK0 Resolution Maximum Setting Time 32 µ...

  • Page 146: Comparator (Mpd17132, 17133, 17P132, And 17P133 Only)

    CHAPTER 13 PERIPHERAL HARDWARE 13.2 COMPARATOR ( µ PD17132, 17133, 17P132, AND 17P133 ONLY) The comparator of the µ PD17132, 17133, 17P132, and 17P133 compares the analog input (Cin to Cin ) and reference voltage (external: 1 type, internal: 15 types) and stores the comparison result to CMPRSLT (RF: 1EH, bit 0). The comparator can also be used as a 4-bit A/D converter by software using 15 types of internal reference voltage.

  • Page 147: Functions Of Comparator

    CHAPTER 13 PERIPHERAL HARDWARE 13.2.2 Functions of Comparator The comparator has a 4-channel analog input. Concerning the pins used as analog input of the comparator, set 1 to P0CnIDI (n=0 to 3) at initial setting of the program (refer to CHAPTER 12 PORTS). One of analog inputs (Cin to Cin ) can be selected by the comparator input channel selection flag (CMPCH1,...
  • Page 148 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-9. Comparator Input Channel Selection Register RF: 1CH Bit 3 Bit 2 Bit 1 Bit 0 CMPCH1 CMPCH0 Read/write Read=R, write=W Initial value when reset CMPCH1 CMPCH0 Comparator Input Channel Selection Select Cin Select Cin Select Cin Select Cin Figure 13-10.
  • Page 149 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-11. Comparator Operation Control Register RF: 1EH Bit 3 Bit 2 Bit 1 Bit 0 CMPSTRT CMPRSLT Read = R, write = W Read/write Initial value when reset CMPRSLT Comparator Operation Comparison Result When the voltage from analog input (Cin to Cin ) is lower than the external/internal reference voltage...

  • Page 150: Serial Interface (Sio)

    CHAPTER 13 PERIPHERAL HARDWARE 13.3 SERIAL INTERFACE (SIO) The serial interfaces of the µ PD17120 subseries consists of a shift register (SIOSFR, 8 bits), serial mode register, and serial clock counter. It is used for serial data input/output. 13.3.1 Functions of the Serial Interface This serial interface provides three signal lines: serial clock input pin (SCK), serial data output pin (SO), and serial data input pin (SI).
  • Page 151 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-12. Block Diagram of the Serial Interface Shift register (SIOSFR) SIOTS SIOHIZ SIOCK1 SIOCK0 IRQSIO clear signal Note Output latch shot IRQSIO /SCK Serial clock counter set signal Carry Clock Clear Output latch Selector SIOEN P0DBIO0 P0DBIO1 Note The output latch of the shift register is common with the output latch of P0D...

  • Page 152: 3-Wire Serial Interface Operation Modes

    CHAPTER 13 PERIPHERAL HARDWARE 13.3.2 3-wire Serial Interface Operation Modes Two modes can be used for the serial interface. If the serial interface function is selected, the P0D /SI pin always takes in data in synchronization with the serial clock. •...
  • Page 153 CHAPTER 13 PERIPHERAL HARDWARE (2) 8-bit receive mode (SO pin: high impedance state) When SIOHIZ=1, the P0D /SO pin is placed in the high-impedance state. At this time, if "1" is written into SIOTS to start supply of the serial clock, the serial interface operates only the receiving function. Because the P0D /SO pin is placed in the high-impedance state, it can be used as an input port (P0D Figure 13-14.
  • Page 154 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-15. Serial Interface Control Register (1/2) RF: 1AH Bit 3 Bit 2 Bit 1 Bit 0 SIOTS SIOHIZ SIOCK1 SIOCK0 Read = R, write = W Read/write Initial value when reset SIOCK1 SIOCK0 Serial Clock Selection External clock (SCK pin) /128 /1024...
  • Page 155 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-15. Serial Interface Control Register (2/2) RF: 0AH Bit 3 Bit 2 Bit 1 Bit 0 SIOEN Read = R, write = W Read/write Initial value when reset Serial Interface Enable SIOEN The pins of port 0D (P0D /SCK, P0D /SO, P0D /SI)

  • Page 156: Setting Values In The Shift Register

    CHAPTER 13 PERIPHERAL HARDWARE 13.3.3 Setting Values in the Shift Register Values are set in the shift register via the data buffer (DBF) using the PUT instruction. The peripheral address of the shift register is 01H. When sending a value to the shift register using the PUT instruction, only the low-order eight bits (DBF1, DBF0) of DBF are valid.

  • Page 157: Reading Values From The Shift Register

    CHAPTER 13 PERIPHERAL HARDWARE 13.3.4 Reading Values from the Shift Register A value is read from the shift register via the data buffer (DBF) using the GET instruction. The shift register has peripheral address 01H and only the eight low-order bits (DBF1, DBF0) are valid. Executing the GET instruction does not affect the eight high-order bits of DBF.

  • Page 158: Program Example Of Serial Interface

    CHAPTER 13 PERIPHERAL HARDWARE 13.3.5 Program Example of Serial Interface (1) Program example of data transmission/reception by 8-bit transmission/reception mode (synchronous transmission/reception) This program executes data transmission/reception synchronizing with f /128. Judgment of finishing serial data transmission/reception is executed by checking interrupt request flag. Example MAIN: CALL...
  • Page 159 CHAPTER 13 PERIPHERAL HARDWARE (2) Program example of data reception by 8-bit reception mode This program executes data reception synchronizing with external clock, and reads reception data by using interrupt processing. Example SIODATH 0.50H SIODATL 0.51H SIO_INIT SIOJOB SIO_INIT: SIODATH, #0H SIODATL, #0H CLR1 IRQSIO...

  • Page 160: Chapter 14 Interrupt Functions

    CHAPTER 14 INTERRUPT FUNCTIONS The µ PD17120 subseries has two internal interrupt functions and one external interrupt function. It can be used in various applications. The interrupt control circuit of this product has the features listed below. This circuit enables very high-speed interrupt handling.

  • Page 161: Interrupt Sources And Vector Address

    CHAPTER 14 INTERRUPT FUNCTIONS 14.1 INTERRUPT SOURCES AND VECTOR ADDRESS For every interrupt in the µ PD17120 subseries, when the interrupt is accepted, a branch occurs to the vector address associated with the interrupt source. This method is called the vectored interrupt method. Table 14-1 lists the interrupt sources and vector addresses.

  • Page 162: Hardware Components Of The Interrupt Control Circuit

    CHAPTER 14 INTERRUPT FUNCTIONS 14.2 HARDWARE COMPONENTS OF THE INTERRUPT CONTROL CIRCUIT The flags of the interrupt control circuit are explained below. 14.2.1 Interrupt Request Flag (IRQ×××) and the Interrupt Enable Flag (IP×××) The interrupt request flag (IRQ×××) is set to 1 when an interrupt request occurs. When interrupt handling is executed, the flag is automatically cleared to 0.
  • Page 163 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (1/4) RF: 0FH Bit 3 Bit 2 Bit 1 Bit 0 Read/write Read=R, write=W Initial value when reset Note State of INT Pin INT pin noise elimination circuit sets logical status to 0 during PEEK instruction execution.
  • Page 164 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (2/4) RF: 3FH Bit 3 Bit 2 Bit 1 Bit 0 Read/write Read=R, write=W Initial value when reset INT Pin Interrupt Request (at Reading) No interrupt request has been issued from the INT pin or an INT pin interrupt is being handled.
  • Page 165 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (3/4) RF: 3DH Bit 3 Bit 2 Bit 1 Bit 0 IRQSIO Read/write Read=R, write=W Initial value when reset IRQSIO SIO Interrupt Request (at Reding) No interrupt request has been issued from the serial interface or a serial interface interrupt is being handled.
  • Page 166 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (4/4) RF: 2FH Bit 3 Bit 2 Bit 1 Bit 0 IPSIO IPTM Read/write Read=R, write=W Initial value when reset INT Pin Interrupt Enable Disables an interrupt from the INT pin. Holds interrupt handling when the IRQ flag is set to 1.

  • Page 167: Interrupt Sequence

    CHAPTER 14 INTERRUPT FUNCTIONS 14.3 INTERRUPT SEQUENCE 14.3.1 Acceptance of Interrupts The moment an interrupt is accepted, the instruction cycle of the instruction which has been executed is terminated, and the interrupt operation is started thus altering the flow of the program to the vector address. However, if the interrupt occurs during execution of the MOVT instruction, the EI instruction or an instruction which has satisfied the skip condition, the processing of this interrupt is started after two instruction cycles are completed.
  • Page 168 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-2. Interrupt Handling Procedure Interrupt request generation Set IRQ××× IP××× set? Hold interrupt until IP××× is set EI instruction executed? (INTE=1?) Hold interrupt until EI instruction is executed Clear INTE flat and IRQ××× associated with accepted interrupt to 0 Decrement stack pointer by 1 (SP-1) Save contents of program counter in stack...

  • Page 169: Return From The Interrupt Routine

    CHAPTER 14 INTERRUPT FUNCTIONS 14.3.2 Return from the Interrupt Routine Execute the RETI instruction to return from the interrupt handling routine. During the RETI instruction cycle, processing in the figure below occurs. Figure 14-3. Return from Interrupt Handling Execute RETI instruction Load contents of stack pointed to by stack pointer into program counter Load contents of interrupt-dedicated stack...

  • Page 170: Interrupt Acceptance Timing

    CHAPTER 14 INTERRUPT FUNCTIONS 14.3.3 Interrupt Acceptance Timing Figure 14-4 shows the interrupt acceptance timing chart. The µ PD17120 subseries executes an instruction with 16 clocks, which is one instruction cycle. One instruction cycle is subdivided into M0-M3 in terms of 4 clocks as a unit.
  • Page 171 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-4. Interrupt Acceptance Timing Chart (when INTE=1, IP×××=1) (2/3) <4> When an interrupt has occurred before M2 of a MOVT instruction Machine cycle Vector address Instruction MOVT instruction INT cycle instruction Interrupt occurrence recognized IRQ××× <5>...
  • Page 172 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-4. Interrupt Acceptance Timing Chart (INTE=1 and IP×××=1) (3/3) <8> When an interrupt has occurred during skipping (NOP handling) by a skip instruction Machine cycle Vector address Instruction Skip instruction Handled as NOP INT cycle instruction Interrupt occurrence recognized IRQ×××...

  • Page 173: Program Example Of Interrupt

    CHAPTER 14 INTERRUPT FUNCTIONS 14.4 PROGRAM EXAMPLE OF INTERRUPT • Program example of contermeasure for noise reduction of external interrupt (INT pin) This example assumes the case of assigning INT pin for key input, etc. When taking into the microcontroller data in kind of switch such as key input processing, it takes some time for the level of input voltage to be stabilized after pushing the key or switch.
  • Page 174 CHAPTER 14 INTERRUPT FUNCTIONS INT_JOB: ; Loop which executes waiting for 100 µ s at 8 MHz ; 2 µ s (1 instruction) × 5 instructions × 10 times ; (count value at WAIT) WAITCNT, #01 WAITCNT, #0AH ; INT_JOB SKF1 ;...
  • Page 175 [MEMO]...

  • Page 176: Chapter 15 Standby Functions

    CHAPTER 15 STANDBY FUNCTIONS 15.1 OUTLINE OF STANDBY FUNCTION The µ PD17120 subseries reduces current consumption by using a standby function. In standby mode, the series uses STOP mode or HALT mode depending on the application. STOP mode is a mode that stops the system clock. In this mode, the CPU's current consumption is mostly limited to the leakage current.
  • Page 177 CHAPTER 15 STANDBY FUNCTIONS Table 15-1. States during Standby Mode STOP mode HALT Mode Instruction to set STOP instruction HALT instruction Clock Oscillation Circuit Oscillation stopped Oscillation continued Operation • Operation stopped Statuses • Immediately-preceding status retained Note 1 Port •...

  • Page 178: Halt Mode

    CHAPTER 15 STANDBY FUNCTIONS 15.2 HALT MODE 15.2.1 HALT Mode Setting The system is placed in HALT mode by executing the HALT instruction. The HALT instruction's operands b are the conditions for canceling HALT mode. Table 15-2. HALT Mode Cancellation Condition Format: HALT b Note 1 Condition for Canceling HALT Mode...
  • Page 179 CHAPTER 15 STANDBY FUNCTIONS Figure 15-1. Cancellation of HALT Mode HALT cancellation by RESET input Execution of the HALT instruction TM count up RESET Operation HALT mode System reset srtate WAIT a Operation mode mode (Start of address 0) WAIT a: This refers to the wait time until TM counts the divide-by-256 clock up to 256. 256 ×...

  • Page 180: Halt Setting Condition

    CHAPTER 15 STANDBY FUNCTIONS 15.2.3 HALT Setting Condition Forced cancellation by IRQTM • The timer is in the operable state (TMEN=1) • The timer's interrupt request flag is cleared (IRQTM=0). Cancellation by the interrupt request flag (IRQ×××) • Setting in a way that places beforehand the peripheral hardware used for HALT cancellation in an operable state.
  • Page 181 CHAPTER 15 STANDBY FUNCTIONS Example 1. A correct program example (Setting of IRQ×××) CLR1 IRQ××× ; Codes a NOP instruction immediately before the HALT instruction ; (Clearance of IRQ××× is reflected correctly to the HALT instruction. HALT 1000B ; Executes the HALT instruction correctly (placing the system in HALT mode). An incorrect program example (Setting of IRQ×××) CLR1...

  • Page 182: Stop Mode

    CHAPTER 15 STANDBY FUNCTIONS 15.3 STOP MODE 15.3.1 STOP Mode Setting Executing the STOP instruction places the system in STOP mode. Operand b of the STOP instruction is the condition for canceling STOP mode. Table 15-4. STOP Mode Cancellation Condition Format: STOP b Note 1 STOP Mode Cancellation Condition...
  • Page 183 CHAPTER 15 STANDBY FUNCTIONS Figure 15-2. Cancellation of STOP Mode STOP cancellation by RESET input Execution of the STOP instruction TM count up RESET Operation STOP mode System reset state WAIT b Operation mode mode (Start of address 0) WAIT b: This refers to the wait time until TM counts the divide-by-256 clock up to 256. 256 ×...

  • Page 184: Stop Setting Condition

    CHAPTER 15 STANDBY FUNCTIONS 15.3.3 STOP Setting Condition Cancellation by IRQ××× Cancellation by IRQ • Sets the edge selection (IEGMD1, IEGMD0) for the signal that is input from the INT pin. • Sets the modulo register value of the timer (wait time for generation of oscillation stability).
  • Page 185 CHAPTER 15 STANDBY FUNCTIONS Example 1. A correct program example (Setting of IRQ×××) CLR1 IRQ××× ; Codes a NOP instruction immediately before the STOP instruction. ; (Clearance of IRQ××× is reflected correctly to the STOP instruction. STOP 1000B ; Executes the STOP instruction correctly (placing the system in STOP mode). An incorrect program example (Setting of IRQ×××) CLR1...

  • Page 186: Chapter 16 Reset

    CHAPTER 16 RESET The following 3 types of resets are provided in the µ PD17120 series. <1> Reset by input to RESET. <2> The power-on/power-down reset function when power is turned on or supply voltage drops. <3> The address stack overflow/underflow reset function. 16.1 RESET FUNCTIONS The reset functions are used to initialize device operations.

  • Page 187: Resetting

    CHAPTER 16 RESET Figure 16-1. Reset Block Configuration Internal bus RF : 10H PDRESEN Internal reset signal Clear signal Oscillation Low-voltage detection circuit disabled Power-on reset circuit Note Mask option RESET Note The µ PD17P132 and 17P133 have no pull-up resistor by mask option, and are always open. 16.2 RESETTING Operation when reset is caused by the RESET input is shown in the figure below.

  • Page 188: Power-On/Power-Down Reset Function

    CHAPTER 16 RESET 16.3 POWER-ON/POWER-DOWN RESET FUNCTION The µ PD17120 subseries is provided with two reset functions to prevent malfunctions from occurring in the microcontroller. They are the power-on reset function and power-down reset function. The power-on reset function resets the microcontroller when it detects that power was turned on. The power-down reset function resets the microcontroller when it detects drops in the power voltage.

  • Page 189: Description And Operation Of The Power-On Reset Function

    CHAPTER 16 RESET 16.3.2 Description and Operation of the Power-On Reset Function The power-on reset function resets the microcontroller when it detects that power was turned on in the hardware, regardless of the software state. The power-on reset circuit operates under a lower voltage than the other internal circuits in the µ PD17120 subseries. It initializes the microcontroller regardless whether the oscillation circuit is operating.
  • Page 190 CHAPTER 16 RESET Figure 16-3. Example of the Power-On Reset Operation A : Voltage at which oscillation starts B : Voltage at which the power-on reset operation terminates µ RESET PD17120 Subseries Time (t) Oscillating Oscillation stop State of oscillation Oscillation start Timer finishes counting Period in which...

  • Page 191: Condition Required For Use Of The Power-Down Reset Function

    CHAPTER 16 RESET 16.3.3 Condition Required for Use of the Power-Down Reset Function The power-down reset function can be enabled or disabled using software. The following conditions are required to use this function: • The power voltage must be 4.5 to 5.5 V during normal operation, including the standby state. Note •...
  • Page 192 CHAPTER 16 RESET Figure 16-4. Example of the Power-Down Reset Operation Maximum voltage detected by the power-down reset function: 4.5V Typical voltage detected by the power-down reset function: 3.5V Voltage at which the power-down µ RESET PD17120 reset function terminates= Subseries power-on reset voltage (B): C Time (t)
  • Page 193 CHAPTER 16 RESET Figure 16-5. Example of Reset Operation during the Period from Power-Down Reset to Power Recovery Maximum voltage detected by the power-down reset function: 4.5V Typical voltage detected by the power-down reset function: 3.5V Voltage at which the power-down reset function terminates= power-on reset voltage (B): C Time (t)

  • Page 194: Chapter 17 One-Time Prom Writing/Verifying

    CHAPTER 17 ONE-TIME PROM WRITING/VERIFYING The on-chip program memory of the µ PD17P132 and 17P133 is a 1024 × 16-bit one-time PROM. Pins listed in Table 17-1 are used for one-time PROM writing/verifying. The address is updated by the clock signal input from the CLK pin.

  • Page 195: Operating Mode In Program Memory Writing/Verifying

    CHAPTER 17 ONE-TIME PROM WRITING/VERIFYING Table 17-2. Differences Between Mask ROM Version and One-Time PROM Version µ PD17120 µ PD17132 µ PD17P132 µ PD17121 µ PD17133 µ PD17P133 Item Mask ROM One-time PROM Mask ROM One-time PROM 768 × 16 bit 1024 ×...

  • Page 196: Writing Procedure Of Program Memory

    CHAPTER 17 ONE-TIME PROM WRITING/VERIFYING 17.3 WRITING PROCEDURE OF PROGRAM MEMORY The program memory can be written at high speeds in the following procedure. Pull down the unused pins to GND. (X pin is open.) Mask the CLK pin low. Apply 5 V to the V pin.

  • Page 197: Reading Procedure Of Program Memory

    CHAPTER 17 ONE-TIME PROM WRITING/VERIFYING Figure 17-1. Procedure of program Memory Writing Repeat × times Reset Additional Address Write Verify writing increment Hi-Z Hi-Z Hi-Z Hi-Z Input data Input data Output data 0– 17.4 READING PROCEDURE OF PROGRAM MEMORY Pull down the unused pins to GND. (X pin is open.) Make the CLK pin low.
  • Page 198 CHAPTER 17 ONE-TIME PROM WRITING/VERIFYING Figure 17-2 shows the program reading procedure (2) through (9). Figure 17-2. Procedure of Program Memory Reading Reset Hi-Z Hi-Z Output data Output data 0– "L"...
  • Page 199 [MEMO]...

  • Page 200: Chapter 18 Instruction Set

    CHAPTER 18 INSTRUCTION SET 18.1 OVERVIEW OF THE INSTRUCTION SET 0000 r, m m, #n4 0001 r, m m, #n4 0010 ADDC r, m ADDC m, #n4 0011 SUBC r, m SUBC m, #n4 0100 r, m m, #n4 0101 r, m m, #n4 0110...

  • Page 201: Legend

    CHAPTER 18 INSTRUCTION SET 18.2 LEGEND Address register Address stack register indicated by stack pointer addr Program memory address (11 bits, the most-significant bit is fixed to 0) BANK Bank register Compare flag Carry flag Data buffer Halt release condition INTEF Interrupt enable flag INTR...

  • Page 202: List Of The Instruction Set

    CHAPTER 18 INSTRUCTION SET 18.3 LIST OF THE INSTRUCTION SET Machine Code Group Mnemonic Operand Operation OP Code Operand (r) ← (r) + (m) r, m 00000 (m) ← (m) + n4 m, #n4 10000 (r) ← (r) + (m) + CY ADDC r, m 00010...

  • Page 203: Assembler (As17K) Macro Instructions

    CHAPTER 18 INSTRUCTION SET Machine Code Group Mnemonic Operand Operation OP Code Operand SP ← SP – 1, ASR ← AR Transfer PUSH 00111 1101 0000 AR ← ASR, SP ← SP + 1 00111 1100 0000 WR ← (rf) PEEK WR, rf 00111...

  • Page 204: Instructions

    CHAPTER 18 INSTRUCTION SET 18.5 INSTRUCTIONS 18.5.1 Addition Instructions Add r, m Add data memory to general register <1> OP code 00000 <2> Function When CMP=0, (r) ← (r) + (m) Adds the data memory contents to the general register contents, and stores the result in general register. When CMP=1, (r) + (m) The result is not stored in the register.
  • Page 205 CHAPTER 18 INSTRUCTION SET If the addition result is zero, with the compare flag reset (CMP=0), the zero flag Z is set. If the addition result is zero, with the compare flag set (CMP=1), the zero flag Z is not changed. Addition can be executed in binary 4-bit or BCD.
  • Page 206 CHAPTER 18 INSTRUCTION SET RP (general register pointer) is assigned in the system register, as shown above. Therefore, to set bank 0 and row address 2 in a general register, 00H must be stored in RPH and 04H, in RPL. In this case, the subsequent arithmetic operation is executed in binary 4-bit operation, because the BCD flag is reset.
  • Page 207 CHAPTER 18 INSTRUCTION SET BANK, #00H RPH, #00H ; General register bank 0 RPL, #00H ; General register row address 0 ; IX ← 00000010000B (0.10H) Note IXH, #00H IXM, #01H IXL, #00H ; IXE flag ← 1 SET1 MEM003, MEM02F ; IX 00000010000B (0.10H) ;...
  • Page 208 CHAPTER 18 INSTRUCTION SET ADD m, #n4 Add immediate data to data memory <1> OP code 10000 <2> Function When CMP=0, (m) ← (m) + n4 Adds immediate data to the data memory contents, and stores the result in data memory. When CMP=1, (m) + n4 The result is not stored in the data memory.
  • Page 209 CHAPTER 18 INSTRUCTION SET (0.6FH) ← (0.6FH) + 05H Address obtained as result of ORing index register contents, 0.40H, and data memory address 0.2FH MEM02F 0.2FH BANK, #00H ; Data memory bank 0 ; IX ← 00001000000B (0.40H) IXH, #00H IXM, #04H IXL, #00H ;...
  • Page 210 CHAPTER 18 INSTRUCTION SET ADDC r, m Add data memory to general register with carry flag <1> OP code 00010 <2> Function When CMP=0, (r) ← (r) + (m) +CY Adds the data memory contents to the general register contents with carry flag CY, and stores the result in general register indentified as r.
  • Page 211 CHAPTER 18 INSTRUCTION SET MEM02D 0.2DH MEM02E 0.2EH MEM02F 0.2FH BANK, #00H ; Data memory bank 0 RPH, #00H ; General register bank 0 RPL, #00H ; General register row address 0 MEM00F, MEM02F ADDC MEM00E, MEM02E ADDC MEM00D, MEM02D Example 2 Shifts the 12-bit contents for addresses 0.2DH through 0.2FH and the carry flag by 1 bit to the left, when row address 2 in bank 0 (0.20H-0.2FH) is specified as a general register.
  • Page 212 CHAPTER 18 INSTRUCTION SET (0.0FH) ← (0.0FH) + (0.40H) + (0.41H) + … + (0.4FH) MEM00F 0.0FH MEM000 0.00H BANK, #00H ; Data memory bank 0 RPH, #00H ; General register bank 0 RPL, #00H ; General register row address 0 ;...
  • Page 213 CHAPTER 18 INSTRUCTION SET ADDC MEM00E, MEM001 ; (0.0EH) ← (0.0EH) + (0.41H) ADDC MEM00F, MEM002 ; (0.0FH) ← (0.0FH) + (0.42H) ADDC m, #n4 Add immediate data to data memory with carry flag <1> OP code 10010 <2> Function When CMP=0, (m) ←...
  • Page 214 CHAPTER 18 INSTRUCTION SET MEM00F 0.0FH BANK, #00H ; Data memory bank 0 MEM00F, #05H ADDC MEM00E, #00H ADDC MEM00D, #00H Example 2 Adds 5 to the 12-bit contents for addresses 0.4DH through 0.4FH, and stores the result in addresses 0.4DH through 0.4FH;...
  • Page 215 CHAPTER 18 INSTRUCTION SET <3> Example 1 Adds 1 to the 16-bit contents for AR3 through AR0 (address registers) in the system register and stores the result in AR3 through AR0: AR0 ← AR0 + 1 AR1 ← AR1 + CY AR2 ←...
  • Page 216 CHAPTER 18 INSTRUCTION SET ; Increments address register by 1 LOOP <4> Note The higher 6 bits of address register are fixed to 0. Only lower 10 bits can be used. INC IX Increment index register <1> OP code 00111 1000 0000 <2>...

  • Page 217: Subtraction Instructions

    CHAPTER 18 INSTRUCTION SET MEM000, #00H ; Writes 0 to data memory indicated by index register ; IXE flag ← 0 CLR1 ; CMP flag ← 1, Z flag ← 1 SET2 CMP, Z IXL, #03H ; Checks whether index register contents SUBC IXM, #07H ;...
  • Page 218 CHAPTER 18 INSTRUCTION SET <3> Example 1 Subtracts the address 0.2FH contents from the address 0.03H contents, and stores the result in address 0.03H, when row address 0 (0.00H-0.0FH) in bank 0 is specified as a general register (RPH=0, RPL=0): (0.03H) ←...
  • Page 219 CHAPTER 18 INSTRUCTION SET ; IXE flag ← 1 SET1 MEM003, MEM02F ; IX 00001000000B (0.40H) ; Bank operand OR) 00000101111B (0.2FH) ; Specified address 00001101111B (0.6FH) Example 4 Subtracts the address 0.3FH contents from the address 0.03H contents and stores the result in address 0.03H.
  • Page 220 CHAPTER 18 INSTRUCTION SET SUB m, #n4 Subtract immediate data from data memory <1> OP code 10001 <2> Function When CMP=0, (m) ← (m) – n4 Subtracts immediate data from the data memory contents, and stores the result in data memory. When CMP=0, (m) –...
  • Page 221 CHAPTER 18 INSTRUCTION SET (0.6FH) ← (0.6FH) – 5 Address obtained as a result of ORing index register contents, 0.40H, and data memory address 0.2FH MEM02F 0.2FH BANK, #00H ; Data memory bank 0 ; IX ← 00001000000B (0.40H) IXH, #00H IXM, #04H IXL, #00H ;...
  • Page 222 CHAPTER 18 INSTRUCTION SET SUBC r, m Subtract data memory from general register with carry flag <1> OP code 00011 <2> Function When CMP=0, (r) ← (r) – (m) – CY Subtracts the data memory contents and the value of carry flag CY from the general register contents. Stores the result in general register.
  • Page 223 CHAPTER 18 INSTRUCTION SET MEM02D 0.2DH MEM02E 0.2EH MEM02F 0.2FH MEM00F, MEM02F SUBC MEM00E, MEM02E SUBC MEM00D, MEM02D Example 2 Subtracts the 12-bit contents for addresses 0.40H through 0.42H from the 12-bit contents for addresses 0.0DH through 0.0FH, and stores the result in 12 bits for addresses 0.0DH through 0.0FH. (0.0DH) ←...
  • Page 224 CHAPTER 18 INSTRUCTION SET MEM00C 0.0CH MEM00D 0.0DH MEM00E 0.0EH MEM00F 0.0FH ; CMP flag ← 1, Z flag ← 1 SET2 CMP, Z MEM000, MEM00C ; Contents for addresses 0.00H-0.03H do not change, SUBC MEM001, MEM00D ; because CMP flag is set SUBC MEM002, MEM00E ;...
  • Page 225 CHAPTER 18 INSTRUCTION SET If the subtraction result is zero, with the compare flag reset (CMP=0), the zero flag Z is set. If the subtraction result is zero, with the compare flag set (CMP=1), the zero flag Z is not changed. Subtraction can be executed in binary or BCD.

  • Page 226: Logical Operation Instructions

    CHAPTER 18 INSTRUCTION SET Example 3 Compares the 12-bit contents for addresses 0.00H through 0.03H with immediate data 0A3FH. Jumps to LAB1, if the contents are the same; if not, jumps to LAB2: MEM000 0.00H MEM001 0.01H MEM002 0.02H MEM003 0.03H ;...
  • Page 227 CHAPTER 18 INSTRUCTION SET <3> Example 1 To OR the address 0.03H contents (1010B) and the address 0.2FH contents (0111B) and store the result (1111B) in address 0.03H: (0.03H) ← (0.03H) (0.2FH) Address 03H Address 2FH Address 03H MEM003 0.03H MEM02F 0.2FH MEM003, #1010B...
  • Page 228 CHAPTER 18 INSTRUCTION SET Example 2 Sets all the bits for address 0.03H: MEM003 0.03H MEM003, #1111B MEM003 0.03H MEM003, #0FH AND r, m AND between general register and data memory <1> OP code 00100 <2> Function (r) ← (r) (m) ANDs the general register contents with data memory contents and stores the result in general register.
  • Page 229 CHAPTER 18 INSTRUCTION SET AND m, #n4 AND between data memory and immediate data <1> OP code 10100 <2> Function (m) ← (m) n4 ANDs the data memory contents and immediate data. Stores the result in data memory. <3> Example 1 To reset bit 3 (MSB) for address 0.03H.
  • Page 230 CHAPTER 18 INSTRUCTION SET <2> Function (r) ← (r) Exclusive-ORs (XOR) the general register contents with data memory contents. Stores the result in general register. <3> Example 1 Compares the address 0.03H contents and the address 0.0FH contents. If different bits are found, set and store them in address 0.03H.

  • Page 231: Judgment Instruction

    CHAPTER 18 INSTRUCTION SET XOR m, #n4 Exclusive OR between data memory and immediate data <1> OP code 10101 <2> Function (m) ← (m) Exclusive-ORs the data memory contents and immediate data. Stores the result in data memory. <3> Example Inverts bits 1 and 3 in address 0.03H and store the result in address 03H: Address 03H Address 03H...
  • Page 232 CHAPTER 18 INSTRUCTION SET <3> Example 1 Jumps to AAA, if bit 0 in address 03H is 1; if it is 0, jumps to BBB: 03H, #0001B Example 2 Skips the next instruction, if both bits 0 and 1 in address 03H are 1. 03H, #0011B ×...

  • Page 233: Comparison Instructions

    CHAPTER 18 INSTRUCTION SET Example 2 Skips the next instruction, if both bits 3 and 0 in address 29H are 0. 29H, #1001B × × × : don't care Skip condition Example 3 The results of executing the following two instructions are the same: 34H, #1111B 34H, #00H 18.5.5 Comparison Instructions...
  • Page 234 CHAPTER 18 INSTRUCTION SET SKNE m, #n4 Skip if data memory not equal to immediate data <1> OP code 01011 <2> Function (m) –n4, skip if not zero Skips the next one instruction, if the data memory contents are not equal to the immediate data value (Executes as NOP instruction).
  • Page 235 CHAPTER 18 INSTRUCTION SET SKGE m, #n4 Skip if data memory greater than or equal to immediate data <1> OP code 11001 <2> Function (m) –n4, skip if not borrow Skips the next one instruction, if the data memory contents are equal to or greater than the immediate data value (Executes as NOP instruction).

  • Page 236: Rotation Instructions

    CHAPTER 18 INSTRUCTION SET MEM00F 0.0FH MEM010 0.10H MEM00F, #02H SKLT MEM010, #06H MEM00F, #01H 18.5.6 Rotation Instructions RORC r Rotate right general register with carry flag <1> OP code 00111 0111 <2> Function Rotates the contents of general register indicated by r including carry flag to the right by 1 bit. <3>...

  • Page 237: Transfer Instructions

    CHAPTER 18 INSTRUCTION SET MEM00C 0.0CH MEM00D 0.0DH MEM00E 0.0EH MEM00F 0.0FH RPH, #00H ; General register bank 0 RPL, #00H ; General register row address 0 ; CY flag ← 0 CLR1 RORC MEM00C RORC MEM00D RORC MEM00E RORC MEM00F 18.5.7 Transfer Instructions LD r, m Load data memory to general register...
  • Page 238 CHAPTER 18 INSTRUCTION SET Bank 0 Column address General register System register Example 2 Stores the address 0.6FH contents to address 0.03H. At this time, data memory address 0.6FH can be specified by selecting data memory address 2FH, if IXE=1, IXH=0, IXM=4, and IXL=0, i.e., IX=0.40H. IXH ←...
  • Page 239 CHAPTER 18 INSTRUCTION SET ST m, r Store general register to data memory <1> OP code 11000 <2> Function (m) ← (r) Stores the general register contents to data memory. <3> Example 1 Stores the address 0.03H contents to address 0.2FH: (0.2FH) ←...
  • Page 240 CHAPTER 18 INSTRUCTION SET MEM018 0.18H MEM000 0.00H LOOP1: ; IXE flag ← 1 SET1 MEM018, MEM000 ; (0.1×H) ← (0.00H) ; IXE flag ← 0 CLR1 ; IX ← IX+1 SKGE IXL, #08H LOOP1 Bank 0 Column address General register System register MOV @r, m Move data memory to destination indirect...
  • Page 241 CHAPTER 18 INSTRUCTION SET <3> Example 1 Stores the address 0.20H contents to address 0.2FH with the MPE flag cleared to 0. The transfer destination data memory address is at the same row address as the transfer source, and the column address is specified by the general register contents at address 0.00H.
  • Page 242 CHAPTER 18 INSTRUCTION SET Bank 0 Column address General register System register MOV m, @r Move data memory to destination indirect <1> OP code 11010 <2> Function When MPE=1 (m) ← (MP, (r)) When MPE=0 (m) ← (BANK, m , (r)) Stores the data memory contents addressed by the general register contents to data memory.
  • Page 243 CHAPTER 18 INSTRUCTION SET Bank 0 Column address General register System register Example 2 Stores the address 0.3FH contents to address 0.20H, with the MPE flag set to 1. The row address for the transfer source data memory is specified by the memory pointer MP contents. The column address is specified by the general register contents at address 0.00H.
  • Page 244 CHAPTER 18 INSTRUCTION SET MOV m, #n4 Move immediate data to data memory <1> OP code 11101 <2> Function (m) ← n4 Stores immediate data to data memory. <3> Example 1 Stores immediate data 0AH to data memory address 0.50H: (0.50H) ←...
  • Page 245 CHAPTER 18 INSTRUCTION SET Stores the program memory contents, addressed by address register AR, to data buffer DBF. Since this instruction temporarily uses one stack level, pay attention to nesting such as subroutines and interrupts. <3> Example To transfer 16 bits of table data, specified by the values for address registers AR3, AR2, AR1, and AR0 in the system register, to data buffers DBF3, DBF2, DBF1, and DBF0: ;...
  • Page 246 CHAPTER 18 INSTRUCTION SET <2> Function SP ← SP–1, ASR ← AR Decrements stack pointer SP and stores the address register AR value to address stack register specified by stack pointer. <3> Example 1 Sets 003FH in address register and stores it in stack: AR3, #00H AR2, #00H AR1, #03H...
  • Page 247 CHAPTER 18 INSTRUCTION SET Example 2 Sets the return address for a subroutine in the address register. Returns execution, if a data table exists after a subroutine: Address 0010H CALL SUB1 SUB1: ;** DATA TABLE 0011H DW 1A1FH 0012H DW 002FH 0013H DW 010AH...
  • Page 248 CHAPTER 18 INSTRUCTION SET POP AR Pop address register <1> OP code 00111 1100 0000 <2> Function AR ← ASR, SP ← SP+1 Pops the contents of address stack register indicated by stack pointer to address register AR and then increments stack pointer SP.
  • Page 249 CHAPTER 18 INSTRUCTION SET PEEK WR, rf Peek register file to window register <1> OP code 00111 0011 <2> Function WR ← (rf) Stores the register file contents to window register WR. <3> Example Stores the stack pointer SP contents at address 01H in the register file to the window register: PEEK WR, SP Bank 0 Column address...
  • Page 250 CHAPTER 18 INSTRUCTION SET (10) POKE rf, WR Poke window register to register file <1> OP code 00111 0010 <2> Function (rf) ← WR Stores the window register WR contents to register file. <3> Example 1 Stores immediate data 0FH to P0DBIO for the register file through the window register: WR, #0FH POKE P0DBIO, WR...
  • Page 251 CHAPTER 18 INSTRUCTION SET <4> Note Among register files, data memories can be seen at 40H-7FH (74H-7FH is system register). Therefore, the PEEK and POKE instructions can access addresses 40H through 7FH in each data memory bank, in addition to the register file. For example, these instructions can be used as follows: MEM05F 0.5FH PEEK...
  • Page 252 CHAPTER 18 INSTRUCTION SET Bank 0 Column address Peripheral circit SIOSFR System register <4> Note 1 The data buffer is assigned to addresses 0CH, 0DH, 0EH, and 0FH in bank 0 for the data memory, regardless of the bank register value. Bank 0 Column address System register...
  • Page 253 CHAPTER 18 INSTRUCTION SET (12) PUT p, DBF Put data buffer to peripheral <1> OP code 00111 1010 <2> Function (p) ← DBF Stores the data buffer DBF contents to peripheral register. <3> Example Sets 0AH and 05H to data buffers DBF1 and DBF0, respectively, and transfers them to a peripheral register, shift register (SIOSFR) for serial interface: BANK, #00H...

  • Page 254: Branch Instructions

    CHAPTER 18 INSTRUCTION SET DBF3 DBF2 DBF1 DBF0 Data buffer Don't care Don't care Data of peripheral Actual bits hardware 18.5.8 Branch Instructions BR addr Branch to the address <1> OP code 01100 addr <2> Function PC ← addr Branches to an address specified by addr. <3>...
  • Page 255 CHAPTER 18 INSTRUCTION SET BR @AR Branch to the address specified by address register <1> OP code 00111 0100 0000 <2> Function PC ← AR Branches to the program address, specified by address register AR. <3> Example 1 Sets 003FH in address register AR (AR0-AR3) and jumps to address 003FH by using the BR @AR instruction: ;...

  • Page 256: Subroutine Instructions

    CHAPTER 18 INSTRUCTION SET 0013H 0014H 0015H 0016H 0017H 0018H MEM010 0.10H RPH, #00H ; General register bank 0 RPL, #02H ; General register row address 1 ; AR3 ← 00H Sets AR to 001×H AR3, #00H ; AR2 ← 00H AR2, #00H ;...
  • Page 257 CHAPTER 18 INSTRUCTION SET Increments the program counter PC value, stores it to stack, and branches to a subroutine specified by addr. <3> Example 1 MAIN SUB: CALL SUB1 Example 2 MAIN SUB1: SUB2: SUB3: CALL SUB1 CALL SUB2 CALL SUB3 CALL @AR Call subroutine specified by address register <1>...
  • Page 258 CHAPTER 18 INSTRUCTION SET <3> Example 1 Sets 0020H in address register AR (AR0-AR3) and calls the subroutine at address 0020H with the CALL @AR instruction: ; AR3 ← 00H AR3, #00H ; AR2 ← 00H AR2, #00H ; AR1 ← 02H AR1, #02H ;...
  • Page 259 CHAPTER 18 INSTRUCTION SET ;**Jump table for subroutine Address 0010H SUB1 0011H SUB2 0012H SUB3 0013H SUB4 SUB1: SUB2: SUB3: 0014H SUB5 0015H SUB6 0016H SUB7 0017H SUB8 0018H SUB9 SUB4: SUB5: SUB6: SUB7: SUB8: SUB9: RPH, #00H ; General register bank 0 RPL, #02H ;...
  • Page 260 CHAPTER 18 INSTRUCTION SET Return to the main program from subroutine <1> OP code 00111 1110 0000 <2> Function PC ← ASR, SP ← SP+1 Instruction to return to the main program from a subroutine. Restores the return address, saved to the stack by the CALL instruction, to the program counter. <3>...
  • Page 261 CHAPTER 18 INSTRUCTION SET <3> Example Executes the RET instruction, if the LSB (least significant bit) content for address 25H in the data memory (RAM) is 0. The execution is returned to the instruction next to the CALL instruction. If the LSB is 1, executes the RETSK instruction.

  • Page 262: Interrupt Instructions

    CHAPTER 18 INSTRUCTION SET 18.5.10 Interrupt Instructions Enable Interrupt <1> OP code 00111 1111 0000 <2> Function INTEF ← 1 Enables a vectored interrupt. The interrupt is enabled, after the instruction next to the EI instruction has been executed. <3> Example 1 As shown in the following example, the interrupt request is accepted after the instruction next to that, that has accepted the interrupt, has been completely executed (excluding an instruction that manipulates program Note1...
  • Page 263 CHAPTER 18 INSTRUCTION SET The interrupt accepted in this example (an interrupt request is generated after the EI instruction has been executed and the execution flow shifts to an interrupt service routine) is the interrupt, whose interrupt enable flag (IP×××) is set. The interrupt request generation without the interrupt enable flag set does not change the program flow, after the EI instruction has been executed (therefore, the interrupt is not accepted).

  • Page 264: Other Instructions

    CHAPTER 18 INSTRUCTION SET 18.5.11 Other Instructions STOP s Stop CPU and release by condition s <1> OP code 00111 1111 <2> Function Stops the system clock and places the device in the STOP mode. In the STOP mode, the power dissipation for the device is minimized. The condition, under which the STOP mode is to be released, is specified by operand (s).
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  • Page 266: Chapter 19 Assembler Reserved Words

    CHAPTER 19 ASSEMBLER RESERVED WORDS 19.1 MASK OPTION PSEUDO INSTRUCTIONS To create µ PD17120, 17121, 17132, and 17133 programs, it is necessary to specify whether pins that can have pull-up resistors have pull-up resistors. This is done in the assembler source program using mask option pseudo instructions.

  • Page 267: Mask Option Definition Pseudo Instructions

    CHAPTER 19 ASSEMBLER RESERVED WORDS 19.1.2 Mask Option Definition Pseudo Instructions Table 19-1 lists the pseudo instructions which define the mask options for each pin. Table 19-1. Mask Option Definition Pseudo Instructions Mask Option Number of Operands Parameter Name Pseudo Instruction RESET OPTRES OPEN...
  • Page 268 CHAPTER 19 ASSEMBLER RESERVED WORDS Example of describing mask options RESET pin: Pull-up : Open, P0D : Open, P0D : Pull-up, P0D : Pull-up, : Pull-up, P0E : Open Symbol Mnemonic Operand Comment ; µ PD17133 Setting mask options: OPTION OPTRES PULLUP OPTP0D...

  • Page 269: Reserved Symbols

    CHAPTER 19 ASSEMBLER RESERVED WORDS 19.2 RESERVED SYMBOLS The reserved symbols defined in the µ PD17120 subseries device file (AS1712×, AS1713×) are listed below. 19.2.1 List of Reserved Symbols ( µ PD17120, 17121) System register (SYSREG) Symbol Name Attribute Value Read/Write Description 0.74H...
  • Page 270 CHAPTER 19 ASSEMBLER RESERVED WORDS Port register Symbol Name Attribute Value Read/Write Description P0E1 0.6FH.1 Port 0E bit 1 ....................................P0E0 0.6FH.0 Port 0E bit 0 P0A3 0.70H.3 Port 0A bit 3 ....................................P0A2 0.70H.2 Port 0A bit 2 ....................................P0A1 0.70H.1 Port 0A bit 1...
  • Page 271 CHAPTER 19 ASSEMBLER RESERVED WORDS Register file (control register) (2/2) Symbol Name Attribute Value Read/Write Description IEGMD1 0.9FH.1 INT pin edge detection selection flag bit 1 ....................................IEGMD0 0.9FH.0 INT pin edge detection selection flag bit 0 P0BGIO 0.A4H.0 P0B group input/output selection flag (1= all P0Bs are output ports.) IPSIO 0.AFH.2...
  • Page 272 CHAPTER 19 ASSEMBLER RESERVED WORDS Others Symbol Name Attribute Value Description Fix operand value of PUT, GET, MOVT instructions Fix operand value of INC instruction...
  • Page 273 CHAPTER 19 ASSEMBLER RESERVED WORDS Figure 19-1. Configuration of Control Register ( µ PD17120, 17121) (1/2) Column address address Item Symbol At reset Read/ Write Symbol At reset Read/ Write Symbol At reset Read/ Write Symbol At reset Read/ Write Remark ( ) means the address when using assembler (AS17K).
  • Page 274 CHAPTER 19 ASSEMBLER RESERVED WORDS Figure 19-1. Configuration of Control Register ( µ PD17120, 17121) (2/2) Note Note The INT flag differs depending on the INT pin state at the time.

  • Page 275: List Of Reserved Symbols ( Μ Pd17132, 17133, 17P132, 17P133)

    CHAPTER 19 ASSEMBLER RESERVED WORDS 19.2.2 List of Reserved Symbols ( µ PD17132, 17133, 17P132, 17P133) System register (SYSREG) Symbol Name Attribute Value Read/Write Description 0.74H Address register bits 15 to 12 0.75H Address register bits 11 to 8 0.76H Address register bits 7 to 4 0.77H Address register bits 3 to 0...
  • Page 276 CHAPTER 19 ASSEMBLER RESERVED WORDS Data buffer (DBF) Symbol Name Attribute Value Read/Write Description DBF3 0.0CH DBF bits 15 to 12 DBF2 0.0DH DBF bits 11 to 8 DBF1 0.0EH DBF bits 7 to 4 DBF0 0.0FH DBF bits 3 to 0 Port register Symbol Name Attribute...
  • Page 277 CHAPTER 19 ASSEMBLER RESERVED WORDS Register file (control register) (1/2) Symbol Name Attribute Value Read/Write Description 0.81H Stack pointer SIOEN 0.8AH.0 SIO enable flag 0.8FH.0 INT pin status flag PDRESEN 0.90H.0 Power-down reset enable flag TMEN 0.91H.3 Timer enable flag ....................................
  • Page 278 CHAPTER 19 ASSEMBLER RESERVED WORDS Register file (control register) (2/2) Symbol Name Attribute Value Read/Write Description P0CBIO3 0.B4H.3 input/output selection flag (1=output port) ....................................P0CBIO2 0.B4H.2 input/output selection flag (1=output port) ....................................P0CBIO1 0.B4H.1 input/output selection flag (1=output port) ....................................P0CBIO0 0.B4H.0 input/output selection flag (1=output port)
  • Page 279 CHAPTER 19 ASSEMBLER RESERVED WORDS Figure 19-2. Configuration of Control Register ( µ PD17132, 17133, 17P132, 17P133) (1/2) Column address address Item Symbol At reset Read/ Write Symbol At reset Read/ Write Symbol At reset Read/ Write Symbol At reset Read/ Write Remark ( ) means the address when using assembler (AS17K).
  • Page 280 CHAPTER 19 ASSEMBLER RESERVED WORDS Figure 19-2. Configuration of Control Register ( µ PD17132, 17133, 17P132, 17P133) (2/2) Note The INT flag differs depending on the INT pin state at the time.
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  • Page 282: Appendix A Development Tools

    APPENDIX A DEVELOPMENT TOOLS The following support tools are available for developing programs for the µ PD17120 subseries. Hardware Name Outline In-circuit Emulator IE-17K, IE-17K-ET, and EMU-17K are the in-circuit emulators common to all IE-17K 17K-series products. Note 1 IE-17K-ET IE-17K and IE-17K-ET are used by connecting to the host machine PC-9800 Note 1 EMU-17K...
  • Page 283 APPENDIX A DEVELOPMENT TOOLS Software Name Outline Host Machine Supply Medium Part Number 17K-Series AS17K is an assembler µ S5A10AS17K 5-inch 2HD Assembler which can be used in PC-9800 series MS-DOS (AS17K) common for the 17K series. For program µ S5A13AS17K 3.5-inch 2HD development of the µ...

  • Page 284: Appendix B Ordering Mask Rom

    After developing the program, place an order for the mask ROM version, according to the following procedure: Make reservation when ordering mask ROM. Advice NEC of the schedule for placing an order for the mask ROM. If NEC is not informed in advance, on- time delivery may not be possible.
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  • Page 286: Appendix C Cautions To Take In System Clock Oscillation Circuit Configurations

    APPENDIX C CAUTIONS TO TAKE IN SYSTEM CLOCK OSCILLATION CIRCUIT CONFIGURATIONS The system clock oscillation circuit operates with a ceramic resonator connected to the X1 and X2 pins or with an oscillation resistor connected to the OSC and OSC pins. Figure C-1 shows the externally installed system clock oscillation circuit.
  • Page 287 APPENDIX C CAUTIONS TO TAKE IN SYSTEM CLOCK OSCILLATION CIRCUIT Figure C-2. Unsatisfactory Oscillation Circuit Examples (a) Connecting circuit whose wiring is too long (b) Signal conductors are intersecting PORT Too long (c) Functuating large current located (d) Current flowing in the GND line of the too close to the signal conductor oscillation circuit (Points A and B's potentials change as to point C.)

  • Page 288: Appendix D Instruction List

    APPENDIX D INSTRUCTION LIST MOVT DBF, @AR…229 m, #n4…193 r, m…189 ADDC m, #n4…198 NOP…249 ADDC r, m…195 m, #n4…214 r, m…213 m, #n4…212 r, m…211 addr…239 @AR…240 PEEK WR, rf…234 POKE rf, WR…235 AR…233 CALL addr…217 PUSH AR…230 CALL @AR:…242 p, DBF…238 DI…248...
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This manual is also suitable for:

Mpd17120Mpd17121Mpd17132Mpd17133Mpd17p132Mpd17p133

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