NEC mPD780208 Subseries User Manual page 281

8-bit single-chip microcontrollers
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CHAPTER 14 SERIAL INTERFACE CHANNEL 1
In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmission/reception mode, buffer
RAM operates as follows.
(i) Before transmission/reception (refer to Figure 14-10 (a))
After arbitrary data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data
is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When
transmission of the first byte is completed, receive data 1 (R1) is transferred from SIO1 to the
buffer RAM, and the automatic data transmit/receive address pointer (ADTP) is decremented.
Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1.
(ii) 4th byte transmission/reception point (refer to Figure 14-10 (b))
Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred
from the buffer RAM to SIO1. When transmission of the fourth byte is completed, receive data
4 (R4) is transferred from SIO1 to the buffer RAM, and ADTP is decremented.
(iii) Completion of transmission/reception (refer to Figure 14-10 (c))
When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIO1
to the buffer RAM, and the interrupt request flag (CSIIF1) is set (INTCSI1 generation).
Figure 14-10. Buffer RAM Operation in 6-Byte Transmission/Reception
(in Basic Transmission/Reception Mode) (1/2)
FAFFH
FAC5H
Transmit data 1 (T1)
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
Transmit data 5 (T5)
FAC0H
Transmit data 6 (T6)
(a) Before transmission/reception
User's Manual U11302EJ4V0UM
Receive data 1 (R1)
SIO1
5
ADTP
—1
0
CSIIF1
281

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