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Instruc- Mnemonic
Operands
tion
Group
AND1
CY, saddr.bit
Bit
manipu-
CY, sfr.bit
lation
CY, A.bit
CY, PSW.bit
CY, [HL].bit
OR1
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
XOR1
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
SET1
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CLR1
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
SET1
CY
CLR1
CY
NOT1
CY
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
Remark One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
CHAPTER 20 INSTRUCTION SET
Bytes
Clocks
Note 1
Note 2
CY ← CY
3
6
7
CY ← CY
3
–
7
CY ← CY
2
4
–
CY ← CY
3
–
7
CY ← CY
2
6
7
CY ← CY
3
6
7
CY ← CY
3
–
7
CY ← CY
2
4
–
CY ← CY
3
–
7
CY ← CY
2
6
7
CY ← CY
3
6
7
CY ← CY
3
–
7
CY ← CY
2
4
–
CY ← CY
3
–
7
CY ← CY
2
6
7
(saddr.bit) ← 1
2
4
6
sfr.bit ← 1
3
–
8
A.bit ← 1
2
4
–
PSW.bit ← 1
2
–
6
(HL).bit ← 1
2
6
8
(saddr.bit) ← 0
2
4
6
sfr.bit ← 0
3
–
8
A.bit ← 0
2
4
–
PSW.bit ← 0
2
–
6
(HL).bit ← 0
2
6
8
CY ← 1
1
2
–
CY ← 0
1
2
–
CY ← CY
1
2
–
User's Manual U11302EJ4V0UM
Operation
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
) selected by the processor clock control
CPU
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
0
×
391
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