System Clock And Cpu Clock Switching Procedure; System Clock And Cpu Clock Switching - NEC mPD780208 Subseries User Manual

5.6.2 System clock and CPU clock switching procedure

This section describes the procedure for switching between the system clock and CPU clock.
V
DD
RESET
Interrupt
request
signal
System clock
CPU clock
[1] The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, the main system clock starts oscillating. At this time, the oscillation
17
stabilization time (2
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (6.4 µ s when
operated at 5.0 MHz).
[2] After the lapse of a sufficient time for the V
processor clock control register (PCC) is rewritten and the maximum-speed operation is carried out.
[3] Upon detection of a decrease of the V
switched to the subsystem clock (which must be in an oscillation stable state).
[4] Upon detection of V
DD
oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation,
PCC is rewritten and the maximum-speed operation is resumed.
Caution When the main system clock is stopped and the subsystem clock is operating, switch to the
main system clock after securing the oscillation stabilization time by program.
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CHAPTER 5 CLOCK GENERATOR
Figure 5-10. System Clock and CPU Clock Switching
f
X
Minimum Maximum speed
speed operation
operation
Wait (26.2 ms: @5.0 MHz)
Internal reset operation
/f ) is secured automatically.
X
voltage to increase to enable operation at maximum speeds, the
DD
voltage due to an interrupt request signal, the main system clock is
DD
voltage reset due to an interrupt request signal, bit 7 (MCC) of PCC is set to 0 and
User's Manual U11302EJ4V0UM
f f
X XT
Subsystem clock
operation
f
X
High-speed
operation