PUSH rp instruction
SP
SP – 2
Lower
SP – 2
register pairs
Higher
SP – 1
register pairs
SP
POP rp instruction
Lower
SP
register pairs
Higher
SP + 1
register pairs
SP
SP + 2
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-14. Data to Be Saved to Stack Memory
CALL, CALLF, and
CALLT instructions
SP
SP – 2
SP – 2
SP – 1
SP
Figure 3-15. Data to Be Reset from Stack Memory
SP
SP + 1
SP
SP + 2
User's Manual U11302EJ4V0UM
SP
SP – 3
SP – 3
SP – 2
PC7 to PC0
SP – 1
PC15 to PC8
RET instruction
PC7 to PC0
PC15 to PC8
SP + 1
SP + 2
SP
SP + 3
Interrupt and
BRK instruction
PC7 to PC0
PC15 to PC8
PSW
SP
RETI and RETB
instructions
SP
PC7 to PC0
PC15 to PC8
PSW