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Symbol
7
6
5
DSPM1
DIGS3
DIGS2 DIGS1 DIGS0 DIMS3 DIMS2
DIMS0 Display mode cycle setting
is 1 display cycle. (1 display cycle = 204.8 µ s: when operated at 5.0 MHz)
0
1024/f
X
is 1 display cycle. (1 display cycle = 409.6 µ s: when operated at 5.0 MHz)
1
2048/f
X
DIMS3 DIMS2 DIMS1 VFD output signal cut width
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
DIGS3 DIGS2 DIGS1 DIGS0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Note Static display is possible when display stop is selected, by manipulating the port output latch.
Remark f
:
X
DSPM05: Bit 5 of display mode register 0 (DSPM0)
CHAPTER 15 VFD CONTROLLER/DRIVER
Figure 15-4. Format of Display Mode Register 1
4
3
2
1
0
DIMS1 DIMS0
1/16
2/16
4/16
6/16
8/16
10/16
12/16
14/16
Display digit (display mode 1) DSPM05 = 0
0
Display stopped (static display)
1
2 digits
0
3 digits
1
4 digits
0
5 digits
1
6 digits
0
7 digits
1
8 digits
0
9 digits
1
10 digits
0
11 digits
1
12 digits
0
13 digits
1
14 digits
0
15 digits
1
16 digits
Main system clock oscillation frequency
User's Manual U11302EJ4V0UM
Address
After reset
R/W
F F A 1 H
0 0 H
R/W
Display pattern (display mode 2) DSPM05 = 1
Note
Display stopped (static display)
2 patterns
3 patterns
4 patterns
5 patterns
6 patterns
7 patterns
8 patterns
9 patterns
10 patterns
11 patterns
12 patterns
13 patterns
14 patterns
15 patterns
16 patterns
Note
307
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