Address
Special-Function Register (SFR) Name
FF60H
Serial operating mode register 0
FF61H
Serial bus interface control register
FF62H
Slave address register
FF63H
Interrupt timing specification register
FF68H
Serial operating mode register 1
FF69H
Automatic data transmit/receive control register
FF6AH
Automatic data transmit/receive address pointer
FF6BH
Automatic data transmit/receive interval specification
register
FF80H
A/D converter mode register
FF84H
A/D converter input select register
FFA0H
Display mode register 0
FFA1H
Display mode register 1
FFA2H
Display mode register 2
FFE0H
Interrupt request flag register 0L
FFE1H
Interrupt request flag register 0H
FFE4H
Interrupt mask flag register 0L
FFE5H
Interrupt mask flag register 0H
FFE8H
Priority order specification flag register 0L
FFE9H
Priority order specification flag register 0H
FFECH
External interrupt mode register
Note
Only bit 7 can be manipulated, and only as a read operation.
66
CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special-Function Register List (2/3)
User's Manual U11302EJ4V0UM
Symbol
R/W
Manipulatable
Bit Unit
1 Bit
√
CSIM0
R/W
√
SBIC
SVA
–
√
SINT
√
CSIM1
√
ADTC
ADTP
–
√
ADTI
√
ADM
ADIS
–
∆
Note
DSPM0
DSPM1
–
DSPM2
–
√
xxxx
IF0L
IF0
√
xxxx
IF0H
√
MK0
xxx x
MK0L
√
MK0H
√
PR0
PR0L
√
xxxx
PR0H
INTM0
–
After
Reset
8 Bits 16 Bits
√
–
00H
√
–
√
–
Undefined
√
–
00H
√
–
√
–
√
–
√
–
√
–
01H
√
–
00H
√
–
√
–
√
–
√
√
√
√
√
FFH
√
√
√
√
√
–
00H