NEC mPD780208 Subseries User Manual page 392

Instruc- Mnemonic
tion
Group
Call CALL !addr16
return
CALLF !addr11
CALLT [addr5]
BRK
RET
RETI
RETB
Stack PUSH PSW
manipu-
rp
lation
POP PSW
rp
MOVW SP, #word
SP, AX
AX, SP
Uncondi-
BR !addr16
tional
$addr16
branch
AX
BC $addr16
Condi-
tional
BNC $addr16
branch
BZ $addr16
BNZ $addr16
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
Remark One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
392
CHAPTER 20 INSTRUCTION SET
Operands Bytes
Note 1
3 7
2 5
1 6
1 6
1 6
1 6
1 6
1 2
1 4
1 2
1 4
4 –
2 –
2 –
3 6
2 6
2 8
2 6
2 6
2 6
2 6
User's Manual U11302EJ4V0UM
Clocks
Note 2
(SP–1) ← (PC+3)
–
PC ← addr16, SP ← SP–2
(SP–1) ← (PC+2)
–
← 00001, PC
PC
15–11
SP ← SP–2
(SP–1) ← (PC+1)
–
← (00000000, addr5+1),
PC
H
← (00000000, addr5),
PC
L
SP ← SP–2
(SP–1) ← PSW, (SP–2) ← (PC+1)
–
(SP–3) ← (PC+1)
← (003EH), SP ← SP–3, IE ← 0
PC
L
← (SP+1), PC
– PC
H
SP ← SP+2
← (SP+1), PC
– PC
H
PSW ← (SP+2), SP ← SP+3,
NMIS ← 0
← (SP+1), PC
– PC
H
PSW ← (SP+2), SP ← SP+3
(SP–1) ← PSW, SP ← SP–1
–
(SP–1) ← rp , (SP–2) ← rp
–
H
SP ← SP–2
PSW ← (SP), SP ← SP+1
–
← (SP+1), rp
– rp
H
SP ← SP+2
SP ← word
10
SP ← AX
8
AX ← SP
8
PC ← addr16
–
PC ← PC + 2 + jdisp8
–
← A, PC
– PC
H L
PC ← PC + 2 + jdisp8 if CY = 1
–
PC ← PC + 2 + jdisp8 if CY = 0
–
PC ← PC + 2 + jdisp8 if Z = 1
–
PC ← PC + 2 + jdisp8 if Z = 0
–
) selected by the processor clock control
CPU
Operation
Z AC CY
, (SP–2) ← (PC+3)
,
H L
, (SP–2) ← (PC+2)
,
H L
← addr11,
10–0
, (SP–2) ← (PC+1)
,
H L
,
H
← (003FH),
, PC
L H
← (SP),
L
← (SP),
R
L
← (SP),
R
L
,
L
R
← (SP),
L
← X
Flag
R R
R R
R R