NEC mPD780208 Subseries User Manual page 389

Instruc- Mnemonic Operands
tion
Group
8-bit OR A, #byte
operation
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
XOR A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
CMP A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, [HL+B]
A, [HL+C]
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
3. Except r = A
Remark One instruction clock cycle is one cycle of the CPU clock (f
register (PCC).
CHAPTER 20 INSTRUCTION SET
Bytes
Clocks
Note 1 Note 2
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
User's Manual U11302EJ4V0UM
Operation
A ← A
– byte
(saddr) ← (saddr)
8 byte
A ← A
– r
r ← r
– A
A ← A
5 (saddr)
A ← A
9 (addr16)
A ← A
5 (HL)
A ← A
9 (HL+byte)
A ← A
9 (HL+B)
A ← A
9 (HL+C)
A ← A
– byte
(saddr) ← (saddr)
8
A ← A
– r
r ← r
– A
A ← A
5 (saddr)
A ← A
9 (addr16)
A ← A
5 (HL)
A ← A
9 (HL+byte)
A ← A
9 (HL+B)
A ← A
9 (HL+C)
– A–byte
8 (saddr)–byte
– A–r
– r–A
5 A–(saddr)
9 A–(addr16)
5 A–(HL)
9 A–(HL+byte)
9 A–(HL+B)
9 A–(HL+C)
) selected by the processor clock control
CPU
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
byte
×
×
×
×
×
×
×
×
× ×
× ×
× ×
× ×
× ×
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389
×
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×