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(6) Address match detection method
In the SBI mode, the master transmits a slave address to select a specific slave device.
A match of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave
address transmitted by the master matches the address set to SVA when the wakeup function specification
bit (WUP) = 1.
If bit 5 (SIC) of the interrupt timing specification register (SINT) is set to 1, the wakeup function cannot be used
even if WUP is set to 1 (an interrupt request signal is generated when bus release is detected). To use the
wakeup function, clear SIC to 0.
Cautions 1. Slave selection/non-selection is detected by matching of the slave address received
after bus release (RELD = 1).
For this match detection, the match interrupt request (CSIIF0) of the address to be
generated with WUP = 1 is normally used. Thus, execute selection/non-selection
detection by slave address when WUP = 1.
2. When detecting selection/non-selection without the use of an interrupt request with
WUP = 0, do so by means of transmission/reception of the command preset by
program instead of using the address match detection method.
(7) Error detection
In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that
is, serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following two ways.
(a) Comparison of SIO0 data before transmission to that after transmission
In this case, if the two data differ, a transmit error is judged to have occurred.
(b) Use of the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI
bit (match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is
tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged
to have occurred.
(8) Communication operation
In the SBI mode, the master device normally selects one slave device as the communication target from
among two or more devices by outputting an "address" to the serial bus.
After the communication target device has been determined, commands and data are transmitted/
received and serial communication is realized between the master and slave devices.
Figures 13-26 to 13-29 show data communication timing charts.
Shift operations of serial I/O shift register 0 (SIO0) are carried out at the falling edge of the serial clock (SCK0).
Transmit data is latched into the SO0 latch and is output with the MSB set as the start bit from the SB0/P25
or SB1/P26 pin. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into
SIO0.
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
User's Manual U11302EJ4V0UM
243
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