Watchdog Timer Operations; Watchdog Timer Operation; Watchdog Timer Program Loop Detection Time - NEC mPD780208 Subseries User Manual

9.4 Watchdog Timer Operations

9.4.1 Watchdog timer operation

When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer operates
to detect an inadvertent program loop.
The watchdog timer count clock (program loop detection time interval) can be selected using bits 0 to 2 (TCL20
to TCL22) of timer clock select register 2 (TCL2).
The watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN
to 1 within the set program loop detection time interval. The watchdog timer can be cleared and counting is started
by setting RUN to 1. If RUN is not set to 1 and the program loop detection time elapses, a system reset or a non-
maskable interrupt request is generated according to the value of WDTM bit 3 (WDTM3).
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN
to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Cautions 1. The actual program loop detection time may be shorter than the set time by a maximum
of 0.5%.
2. When the subsystem clock is selected for the CPU clock, the watchdog timer count
operation is stopped.
TCL22
0
0
0
0
1
1
1
1
f : Main system clock oscillation frequency
X
180
CHAPTER 9 WATCHDOG TIMER
Table 9-4. Watchdog Timer Program Loop Detection Time
TCL21 TCL20 Program Loop Detection Time
11
0 0 2 x 1/f
12
0 1 2 x 1/f
13
1 0 2 x 1/f
1 1 2 14 x 1/f
0 0 2 15 x 1/f
0 1 2 16 x 1/f
1 0 2 17 x 1/f
1 1 2 19 x 1/f
User's Manual U11302EJ4V0UM
f
X
410 µ s
X
819 µ s
X
1.64 ms
X
3.28 ms
X
6.55 ms
X
13.1 ms
X
26.2 ms
X
105.0 ms
X
= 5.0 MHz