Wire Serial I/O Mode Timing - NEC mPD780208 Subseries User Manual

8-bit single-chip microcontrollers
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CHAPTER 13 SERIAL INTERFACE CHANNEL 0
(2) Communication operation
The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/
reception is carried out bit by bit in synchronization with the serial clock.
Shift operations of serial I/O shift register 0 (SIO0) are carried out in synchronization with the falling edge
of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/P25
(or SB1/P26) pin with the MSB set as the start bit. The receive data input from the SB0 (or SB1) pin is
latched into SIO0 at the rising edge of SCK0.
Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag
(CSIIF0) is set.
Figure 13-31. 2-Wire Serial I/O Mode Timing
1
2
3
4
5
6
7
8
SCK0
D7
D6
D5
D4
D3
D2
D1
D0
SB0/SB1
CSIIF0
End of transfer
Transfer start at the falling edge of SCK0
The SB0 (SB1) pin specified for the serial data bus is an N-ch open-drain I/O and thus it must be externally
pulled up. Because the N-ch open-drain output must be high impedance for data reception, write FFH
to SIO0 in advance.
The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can
be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the
P27 output latch (refer to 13.4.5 SCK0/P27 pin output manipulation).
253
User's Manual U11302EJ4V0UM

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