Format Of Timer Clock Select Register 2 - NEC mPD780208 Subseries User Manual

8-bit single-chip microcontrollers
Table of Contents

Advertisement

Symbol
7
6
5
TCL2
TCL27
TCL26
TCL25
Note When using a main system clock of 1.25 MHz or less and the VFD controller/driver, select f
the count clock for the watch timer.
Caution
When changing the count clock, be sure to stop operation of the watch timer before
rewriting TCL2 (stopping operation is not necessary when rewriting the same data).
Remarks 1. f
: Main system clock oscillation frequency
X
2. f
: Subsystem clock oscillation frequency
XT
3. x:
4. Figures in parentheses apply to operation with f
CHAPTER 8 WATCH TIMER
Figure 8-2. Format of Timer Clock Select Register 2
4
3
2
1
TCL24
0
TCL22
TCL21
don't care
User's Manual U11302EJ4V0UM
0
Address
After reset
TCL20
FF42H
00H
TCL22
TCL21
TCL20
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TCL24 Watch timer count clock selection
8
0
f
/2
(19.5 kHz)
X
f
(32.768 kHz)
1
XT
TCL27
TCL26
TCL25
×
×
0
1
0
0
1
0
1
1
1
0
1
1
1
= 5.0 MHz or f
X
R/W
R/W
Count clock selection
Watchdog timer mode
Interval timer mode
3
4
f
/2
(625 kHz)
f
/2
(313 kHz)
X
X
4
5
f
/2
(313 kHz)
f
/2
(156 kHz)
X
X
5
6
f
/2
(156 kHz)
f
/2
(78.1 kHz)
X
X
6
7
f
/2
(78.1 kHz)
f
/2
(39.1 kHz)
X
X
7
8
f
/2
(39.1 kHz)
f
/2
(19.5 kHz)
X
X
8
9
f
/2
(19.5 kHz)
f
/2
(9.8 kHz)
X
X
9
10
f
/2
(9.8 kHz)
f
/2
(4.9 kHz)
X
X
11
12
f
/2
(2.4 kHz)
f
/2
(1.2 kHz)
X
X
Note
Buzzer output frequency selection
Buzzer output disabled
10
f
/2
(4.9 kHz)
X
11
f
/2
(2.4 kHz)
X
12
f
/2
(1.2 kHz)
X
Setting prohibited
/2
X
= 32.768 kHz.
XT
8
as
171

Advertisement

Table of Contents
loading

This manual is also suitable for:

Mpd780204Mpd780206Mpd780208Mpd78p0208Mpd780204aMpd780205a ... Show all

Table of Contents