Format Of Timer Clock Select Register 0 - NEC mPD780208 Subseries User Manual

Symbol <7> 6 5
TCL0 CLOE TCL06 TCL05
Cautions 1. The TI0/P00/INTP0 pin valid edge is set by the external interrupt mode register
2. When enabling PCL output, set TCL00 to TCL03, then set CLOE to 1 with a 1-bit
3. To read the count value when TI0 has been specified as the TM0 count clock, the value
4. If TCL0 is to be rewritten with data other than identical data, the timer operation must
Remarks 1. f
2. f
3. TI0: 16-bit timer/event counter input pin
4. TM0: 16-bit timer register
5. Figures in parentheses apply to operation with f
184
CHAPTER 10 CLOCK OUTPUT CONTROLLER
Figure 10-3. Format of Timer Clock Select Register 0
4 3 2 1
TCL04 TCL03 TCL02 TCL01
(INTM0), and the sampling clock frequency is selected by the sampling clock select
register (SCS).
memory manipulation instruction.
should be read from TM0, not from the 16-bit capture register (CR01).
be stopped first.
: Main system clock oscillation frequency
X
: Subsystem clock oscillation frequency
XT
User's Manual U11302EJ4V0UM
0 Address After reset
TCL00 FF40H 00H
TCL03 TCL02 TCL01
0 0 0
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
Other than above
TCL06 TCL05 TCL04
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
Other than above
CLOE PCL output control
0 Output disabled
1 Output enabled
= 5.0 MHz or f
X
R/W
R/W
TCL00 PCL output clock selection
f (32.768 kHz)
0
XT
3
1 f /2 (625 kHz)
X
4
0 f /2 (313 kHz)
X
5
f /2 (156 kHz)
1
X
6
0 f /2 (78.1 kHz)
X
7
f /2 (39.1 kHz)
1
X
8
0 f /2 (19.5 kHz)
X
Setting prohibited
16-bit timer register count clock
selection
TI0 (valid edge specifiable)
f (5.0 MHz)
X
f /2 (2.5 MHz)
X
2
f /2 (1.25 MHz)
X
3
f /2 (625 kHz)
X
Setting prohibited
= 32.768 kHz.
XT