Table 8 External Interrupt Control Registers - Renesas 4513 User Manual

HARDWARE
FUNCTION BLOCK OPERATIONS
(3) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 inter-
rupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.

Table 8 External interrupt control registers

Interrupt control register I1
I1 Not used
3
Interrupt valid waveform for INT0 pin/
I1
2
return level selection bit (Note 2)
I1 INT0 pin edge detection circuit control bit
1
INT0 pin
I1
0
timer 1 control enable bit
Interrupt control register I2
I2
Not used
3
Interrupt valid waveform for INT1 pin/
I2
2
return level selection bit (Note 3)
I2
INT1 pin edge detection circuit control bit
1
INT1 pin
I2
0
timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When the contents of I1
3: When the contents of I2
1-28
is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
2
is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
2
4513/4514 Group User's Manual
• Interrupt control register I2
Register I2 controls the valid waveform for the external 1 inter-
rupt. Set the contents of this register through register A with the
TI2A instruction. The TAI2 instruction can be used to transfer the
contents of register I2 to register A.
at reset : 0000 at RAM back-up : state retained
2
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT0 pin is recognized with the SNZI0
0
instruction)/"L" level
Rising waveform ("H" level of INT0 pin is recognized with the SNZI0
1
instruction)/"H" level
0 One-sided edge detected
1 Both edges detected
0
Disabled
1
Enabled
at reset : 0000 at RAM back-up : state retained
2
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT1 pin is recognized with the SNZI1
0
instruction)/"L" level
Rising waveform ("H" level of INT1 pin is recognized with the SNZI1
1
instruction)/"H" level
0 One-sided edge detected
1 Both edges detected
0 Disabled
1 Enabled
R/W
R/W