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HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS
Interrupt control register V1
V1
Timer 2 interrupt enable bit
3
V1
Timer 1 interrupt enable bit
2
V1
External 1 interrupt enable bit
1
V1
External 0 interrupt enable bit
0
Interrupt control register V2
V2
Serial I/O interrupt enable bit
3
V2
A-D interrupt enable bit
2
V2
Timer 4 interrupt enable bit
1
V2
Timer 3 interrupt enable bit
0
Interrupt control register I1
Not used
I1
3
Interrupt valid waveform for INT0 pin/
I1
2
return level selection bit (Note 2)
I1
INT0 pin edge detection circuit control bit
1
INT0 pin
I1
0
timer 1 control enable bit
Interrupt control register I2
I2
Not used
3
Interrupt valid waveform for INT1 pin/
I2
2
return level selection bit (Note 3)
I2
INT1 pin edge detection circuit control bit
1
INT1 pin
I2
0
timer 3 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled.
2: When the contents of I1
3: When the contents of I2
1-84
is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
2
is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
2
4513/4514 Group User's Manual
at reset : 0000
at reset : 0000
2
2
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
Interrupt disabled (SNZ1 instruction is valid)
1
Interrupt enabled (SNZ1 instruction is invalid)
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 0000
2
0
Interrupt disabled (SNZSI instruction is valid)
1
Interrupt enabled (SNZSI instruction is invalid)
0
Interrupt disabled (SNZAD instruction is valid)
1
Interrupt enabled (SNZAD instruction is invalid)
0
Interrupt disabled (SNZT4 instruction is valid)
1
Interrupt enabled (SNZT4 instruction is invalid)
0
Interrupt disabled (SNZT3 instruction is valid)
1
Interrupt enabled (SNZT3 instruction is invalid)
at reset : 0000
at RAM back-up : state retained
2
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT0 pin is recognized with the SNZI0
0
instruction)/"L" level
Rising waveform ("H" level of INT0 pin is recognized with the SNZI0
1
instruction)/"H" level
0
One-sided edge detected
1
Both edges detected
0
Disabled
1
Enabled
at reset : 0000
at RAM back-up : state retained
2
0
This bit has no function, but read/write is enabled.
1
Falling waveform ("L" level of INT1 pin is recognized with the SNZI1
0
instruction)/"L" level
Rising waveform ("H" level of INT1 pin is recognized with the SNZI1
1
instruction)/"H" level
One-sided edge detected
0
Both edges detected
1
0
Disabled
1
Enabled
at RAM back-up : 0000
at RAM back-up : 0000
2
2
at RAM back-up : 0000
2
R/W
R/W
R/W
R/W
R/W
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