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PIN DESCRIPTION
Name
Pin
V
Power supply
DD
Ground
V
SS
Voltage drop detec-
VDCE
tion circuit enable
CNV
CNV
SS
SS
RESET
Reset input
X
System clock input
IN
X
System clock output
OUT
D
–D
I/O port D
0
7
(Input is examined
by skip decision.)
P0
–P0
I/O port P0
0
3
P1
–P1
I/O port P1
0
3
P2
–P2
Input port P2
0
2
P3
–P3
I/O port P3
0
3
P4
–P4
I/O port P4
0
3
P5
–P5
I/O port P5
0
3
A
–A
Analog input
IN0
IN7
CNTR0
Timer input/output
CNTR1
Timer input/output
INT0, INT1
Interrupt input
S
Serial data input
IN
S
Serial data output
OUT
S
Serial I/O clock
CK
input/output
CMP0-
Voltage comparator
CMP0+
input
CMP1-
Voltage comparator
CMP1+
input
Input/Output
—
Connected to a plus power supply.
Connected to a 0 V power supply.
—
Input
VDCE pin is used to control the operation/stop of the voltage drop detection circuit.
When "H" level is input to this pin, the circuit is operating. When "L" level is inpu to
this pin, the circuit is stopped.
—
Connect CNV
SS
An N-channel open-drain I/O pin for a system reset. When the watchdog timer
I/O
causes the system to be reset or system reset is performed by the voltage drop de-
tection circuit, the RESET pin outputs "L" level.
I/O pins of the system clock generating circuit. X
Input
ceramic resonator. A feedback resistor is built-in between them.
Output
Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out-
I/O
put latch. For input use, set the latch of the specified bit to "1." The output structure
is N-channel open-drain.
Ports D
and D
6
Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs
I/O
when the output latch is set to "1." The output structure is N-channel open-drain.
I/O
Every pin of the ports has a key-on wakeup function and a pull-up function. Both
functions can be switched by software.
3-bit input port. Ports P2
Input
spectively.
4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the
I/O
specified bit to "1." The output structure is N-channel open-drain. Ports P3
P3
are also used as INT0 and INT1, respectively.
1
The 4513 Group does not have ports P3
4-bit I/O port. For input use, set the latch of the specified bit to "1." The output
I/O
structure is N-channel open-drain. Ports P4
pins A
–A
IN4
IN7
The 4513 Group does not have port P4.
I/O
4-bit I/O port. Each pin has a direction register and an independent 1-bit wide I/O
function. For input use, set the direction register to "0." For output use, set the di-
rection regiser to "1." The output structure is CMOS.
The 4513 Group does not have port P5.
Input
Analog input pins for A-D converter. A
tor input pins and A
The 4513 Group does not have A
I/O
CNTR0 pin has the function to input the clock for the timer 2 event counter, and to
output the timer 1 underflow signal divided by 2.
CNTR0 pin is also used as port D
I/O
CNTR1 pin has the function to input the clock for the timer 4 event counter, and to
output the timer 3 underflow signal divided by 2.
CNTR1 pin is also used as port D
Input
INT0, INT1 pins accept external interrupts. They also accept the input signal to re-
turn the system from the RAM back-up state.
INT0, INT1 pins are also used as ports P3
Input
S
pin is used to input serial data signals by software.
IN
S
pin is also used as port P2
IN
Output
S
pin is used to output serial data signals by software.
OUT
S
pin is also used as port P2
OUT
I/O
S
pin is used to input and output synchronous clock signals for serial data trans-
CK
fer by software.
S
pin is also used as port P2
CK
Input
CMP0-, CMP0+ pins are used as the voltage comparator input pin when the volt-
age comparator function is selected by software.
CMP0-, CMP0+ pins are also used as A
Input
CMP1-, CMP1+ pins are used as the voltage comparator input pin when the volt-
age comparator function is selected by software.
CMP1-, CMP1+ pins are also used as A
4513/4514 Group User's Manual
Function
to V
and apply "L" (0V) to CNV
SS
are also used as CNTR0 and CNTR1, respectively.
7
, P2
and P2
are also used as S
0
1
2
, P3
2
, respectively.
–A
IN0
–A
are also used as port P4.
IN4
IN7
–A
.
IN4
IN7
.
6
.
7
0
.
2
.
1
.
0
and A
IN0
and A
IN2
HARDWARE
PIN DESCRIPTION
certainly.
SS
and X
can be connected to
IN
OUT
, S
and S
CK
OUT
.
3
–P4
are also used as analog input
0
3
are also used as voltage compara-
IN3
and P3
, respectively.
1
.
IN1
.
IN3
, re-
IN
and
0
1-9
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