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2.7.2 Internal state at reset
Figure 2.7.3 shows the internal state at reset. The contents of timers, registers, flags and RAM other than
shown in Figure 2.7.3 are undefined, so that set them to initial values.
• Program counter (PC) ............................................................................................
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) ...................................................................................
• Power down flag (P) ...............................................................................................
• External 0 interrupt request flag (EXF0) ................................................................
• External 1 interrupt request flag (EXF1) ................................................................
• Interrupt control register V1 ...................................................................................
• Interrupt control register V2 ...................................................................................
• Interrupt control register I1 ....................................................................................
• Interrupt control register I2 ....................................................................................
• Timer 1 interrupt request flag (T1F) ......................................................................
• Timer 2 interrupt request flag (T2F) ......................................................................
• Timer 3 interrupt request flag (T3F) ......................................................................
• Timer 4 interrupt request flag (T4F) ......................................................................
• Watchdog timer flags (WDF1, WDF2) ...................................................................
• Watchdog timer enable flag (WEF) .......................................................................
• Timer control register W1 ......................................................................................
• Timer control register W2 ......................................................................................
• Timer control register W3 ......................................................................................
• Timer control register W4 ......................................................................................
• Timer control register W6 ......................................................................................
• Clock control register MR ......................................................................................
• Serial I/O transmit/receive completion flag ............................................................
• Serial I/O mode register J1 ....................................................................................
• Serial I/O register SI ..............................................................................................
• A-D conversion completion flag ADF ....................................................................
• A-D control register Q1 ..........................................................................................
• A-D control register Q2 ..........................................................................................
• Voltage comparator control register Q3 ................................................................
• Successive comparison register AD ......................................................................
• Comparator register ...............................................................................................
• Key-on wakeup control register K0 .......................................................................
• Pull-up control register PU0 ...................................................................................
• Direction register FR0 ............................................................................................
• Carry flag (CY) .......................................................................................................
• Register A ..............................................................................................................
• Register B ..............................................................................................................
• Register D ..............................................................................................................
• Register E ..............................................................................................................
• Register X ..............................................................................................................
• Register Y ..............................................................................................................
• Register Z ...............................................................................................................
• Stack pointer (SP) ..................................................................................................
Fig. 2.7.3 Internal state at reset
0
0
0
0
0
0
0
0
0
0
0
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0
0
0
0
0
0
0
0
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1
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1
4513/4514 Group User's Manual
APPLICATION
0
0
0
0
0
0
0
0
0
(Interrupt disabled)
0
0
0
0
0
(Interrupt disabled)
0
0
(Interrupt disabled)
0
0
0
0
0
0
0
0
0
0
0
0
(Prescaler, timer 1 stopped)
0
0
(Timer 2 stopped)
0
0
(Timer 3 stopped)
0
0
(Timer 4 stopped)
0
0
0
0
0
0
0
(External clock selected,
serial I/O port not selected))
0
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0
0
0
0
0
0
0
0
0
0
0
(Port P5 input mode)
0
0
0
0
0
0
0
0
0
1
1
" " represents undefined.
2.7 Reset
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2-57
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