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(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V1
–V1
and V2
0
3
0
"1." The interrupt actually occurs 2 to 3 machine cycles after the
cycle in which all three conditions are satisfied. The interrupt oc-
When an interrupt request flag is set after its interrupt is enabled (Note 1)
f (X
) (middle-speed mode)
IN
f (X
) (high-speed mode)
IN
System clock
Interrupt enable
flag (INTE)
INT0, INT1
External
interrupt
EXF0, EXF1
Timer 1,
Timer 2,
T1F, T2F, T3F,
Timer 3,
T4F, ADF,SIOF
Timer 4,
A-D, and
Serial I/O
interrupts
Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset.
2: The address is stacked to the last cycle.
3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
–V2
), and interrupt request flag are
3
1 machine cycle
T
T
T
T
1
2
3
1
EI instruction
execution cycle
4513/4514 Group User's Manual
FUNCTION BLOCK OPERATIONS
curs after 3 machine cycles only when the three interrupt condi-
tions are satisfied on execution of other than one-cycle instructions
(Refer to Figure 16).
T
T
T
T
T
T
2
3
1
2
3
1
Interrupt enabled state
Interrupt activated
condition is satisfied.
2 to 3 machine cycles
HARDWARE
T
T
T
T
2
3
1
2
Interrupt disabled state
Retaining level of system
clock for 4 periods or more
is necessary.
Flag cleared
The program starts from
the interrupt address.
(Notes 2, 3)
T
3
1-25
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