Related Registers; Table 2.4.1 Serial I/O Mode Register J1 - Renesas 4513 User Manual

2.4.2 Related registers

(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to
register SI through registers A and B with the TSIAB instruction.
(2) Serial I/O mode register J1
Serial I/O synchronous clock selection bit is assigned to bit 0, serial I/O port selection bit is assigned
to bit 1 and serial I/O internal clock dividing ratio selection bit is assigned to bit 2.
Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction
can be used to transfer the contents of register J1 to register A.
Table 2.4.1 shows the serial I/O mode register J1.

Table 2.4.1 Serial I/O mode register J1

Serial I/O mode register J1
J1 Not used
3
Serial I/O internal clock dividing
J1
2
ratio selection bit
J1 Serial I/O port selection bit
1
Serial I/O synchronous clock
J1
0
selection bit
Note: "R" represents read enabled, and "W" represents write enabled.
(3) Serial I/O transmission/reception completion flag (SIOF)
Serial I/O transmission/reception completion flag (SIOF) is set to "1" when serial data transmission
or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI).
at reset : 0000
2
0
This bit has no function, but read/write is enabled.
1
0 Instruction clock signal divided by 8
1 Instruction clock signal divided by 4
Input ports P2
0
Serial I/O ports S
1
0 External clock
1 Internal clock (instruction clock divided by 4 or 8)
4513/4514 Group User's Manual
APPLICATION
at RAM back-up : state retained
, P2 , P2 selected
0 1 2
, S , S /input ports P2
CK OUT IN
2.4 Serial I/O
R/W
, P2 , P2 selected
0 1 2
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